Commit graph

86 commits

Author SHA1 Message Date
cinap_lenrek
2149600d12 kernel: catch execution read fault on SG_NOEXEC segment
fault() now has an additional pc argument that is
used to detect fault on a non-executable segment.
that is, we check on read fault if the segment
has the SG_NOEXEC attribute and the program counter
is within faulting page.
2019-08-27 03:47:18 +02:00
cinap_lenrek
128ea44a89 kernel: expose no execute bit to portable mmu code as SG_NOEXEC / PTENOEXEC, add PTECACHED bits
a portable SG_NOEXEC segment attribute was added to allow
non-executable (physical) segments. which will set the
PTENOEXEC bits for putmmu().

in the future, this can be used to make non-executable
stack / bss segments.

the SG_DEVICE attribute was added to distinguish between
mmio regions and uncached memory. only matterns on arm64.

on arm, theres the issue that PTEUNCACHED would have
no bits set when using the hardware bit definitions.
this is the reason bcm, kw, teg2 and omap kernels use
arteficial PTE constants. on zynq, the XN bit was used
as a hack to give PTEUNCACHED a non-zero value and when
the bit is clear then cache attributes where added to
the pte.

to fix this, PTECACHED constant was added.

the portable mmu code in fault.c will now explicitely set
PTECACHED bits for cached memory and PTEUNCACHED for
uncached memory. that way the hardware bit definitions
can be used everywhere.
2019-08-26 22:34:38 +02:00
cinap_lenrek
51cfe763a4 emmc: 50MHz highspeed support (from richard miller) 2019-08-25 20:02:53 +02:00
cinap_lenrek
bcf988aff1 bcm64: deal with discontinuous memory regions, avoid virtual memory aliasing, implement vmap() proper
on the 2GB and 4GB raspberry pi 4 variants, there are two
memory regions for ram:

[0x00000000..0x3e600000)
[0x40000000..0xfc000000)

the framebuffer is somewhere at the end of the first
GB of memory.

to handle these, we append the region base and limit
of the second region to *maxmem= like:

*maxmem=0x3e600000 0x40000000 0xfc000000

the mmu code has been changed to have non-existing
ram unmapped and mmukmap() now uses small 64K pages
instead of 512GB pages to avoid aliasing (framebuffer).

the VIRTPCI mapping has been removed as we now have
a proper vmap() implementation which assigns vritual
addresses automatically.
2019-08-23 21:39:20 +02:00
cinap_lenrek
e6d22570a8 bcm: invalidate cache on Fbinfo after firmware completion 2019-08-22 02:54:06 +02:00
cinap_lenrek
aca0293f0b bcm: flush out early boot messages on uart and screen initialization
make early boot messages available by writing out
kmesg.buf after uart and screen initialization.
2019-08-22 02:52:21 +02:00
cinap_lenrek
b4cb19235e bcm: set XN bits for kernel device mappings 2019-08-21 18:28:01 +02:00
cinap_lenrek
3fc8d1bdae bcm64: add driver for emmc2 controller 2019-08-18 18:50:24 +02:00
cinap_lenrek
bc8c31dbd5 bcm: fix typo in gpio.c on unused AFedge0 constant 2019-08-16 19:35:46 +02:00
cinap_lenrek
05f9a66fd4 bcm, bcm64: add vcore support for raspberry pi 3 GPIO expander 2019-07-28 11:39:57 +02:00
cinap_lenrek
8630bd35a6 bcm, bcm64: add BCM2711 support for gpiopull(), fix gpiomeminit(), cleanup
according to the following linux change, BCM2711 uses a different
method for changing pullup/down mode:

abcfd09286 (diff-cf078559c38543ac72c5db99323e236d)

gpiomeminit() was broken, using virtual address for the gpio physseg
instead of the physical one.

cleanup the code, avoid repetition by declaring static u32int *regs
variable. make local variable names consistent.
2019-07-27 20:00:53 +02:00
cinap_lenrek
1717368f64 bcm, bcm64: clean dma destination buffer before issuing dma in case of non cache-line-size aligned buffer 2019-07-25 13:55:17 +02:00
cinap_lenrek
811b80cae1 bcm, bcm64: make irq.$O optional and add intrdisable(), use intrenable()
the raspberry pi 4 has a new interrupt controller and
pci support, so get rid of intrenable() macro and
properly make intrenable function with tbdf argument.
2019-07-25 08:58:58 +02:00
cinap_lenrek
5a0c2e2d17 bcm, bcm64: add dmaflush() function and make virtio size and virtual address configurable in Soc.virtio and Soc.iosize 2019-07-25 08:41:37 +02:00
cinap_lenrek
4983adfa2c bcm, bcm64: add support for device tree parameter passing
the new raspberry pi 4 firmware for arm64 seems to have
broken atag support. so we now parse the device tree
structure to get the bootargs and memory configuration.
2019-07-25 08:19:12 +02:00
cinap_lenrek
4d96bacd35 bcm, kw, omap, teg2: implement setregisters() 2019-06-20 13:17:36 +02:00
cinap_lenrek
c881e33e8e bcm, bcm64: fix cache operations for dma and emmc
always clean AND invalidate caches before dma read,
never just invalidate as the buffer might not be
aligned to cache lines...

we have to invalidate caches again *AFTER* the dma
read has completed. the processor can bring in data
speculatively into the cache while the dma in in
flight.
2019-05-19 16:54:50 +02:00
cinap_lenrek
adf96a529e bcm: add cache invalidate before accessing prop buffer 2019-05-13 19:21:14 +02:00
cinap_lenrek
3b36daa2bb bcm, bcm64: preserve memsize across reboots, avoid trashing atags while parsing cmdline
we override atag memory on reboot, so preserve
the memsize learned from atag as *maxmem plan9
variable. the global memsize variable is not
needed anymore.

avoid trashing the following atag when zero
terminating the cmdline string.

zero memory after plan9.ini variables.
2019-05-13 19:12:41 +02:00
cinap_lenrek
75d44bc306 bcm: make sure fiq is on enabled on cpu0 2019-05-05 14:04:27 +02:00
cinap_lenrek
4d96c40a47 usbdwc: enable Slowbuilkin workarround, improve split transaction timing, handle erroring sleep(), debugging
i'v been seeing the error condition described above in the
Slowbulkin comment. so i'm enabling the work arround which
seems to fix the lockup.

in the split transaction case where we want to start the
transaction at frame start, acquire the ctlr lock *before*
checking if we are in the right frame number. so the start
will happen atomically. checking the software ctlr->sofchan
instead of checking the interrupt mask register seems to
be quicker.

setting the haint mask bit for the chan under ctlr lock
in chanio() instead of chanwait() avoids needing to acquire
the ctlr lock twice.

mask wakechan bits with busychan bitmap in interrupt handlers
so we will not try to wake up released chans by accident.

sleep() and tsleep() might get interrupted so we have to
release the split qlock in the split transaction case and
in all cases, make sure to halt the channel before release.

add some common debug functions to dump channel and controller
registers.
2019-05-05 13:34:02 +02:00
cinap_lenrek
1a7c224b3e bcm: don't call nil on PADDR() in dmaaddr(), return busdram dummy address 2019-05-03 22:53:09 +02:00
cinap_lenrek
eb4bd4aa3e bcm: move fiq saved pc adjust into lexception.s so it can be shared with arm64 2019-05-03 22:02:07 +02:00
cinap_lenrek
3ca395a36c uartpl011: dont touch line control while uart is enabled 2019-05-03 21:34:20 +02:00
cinap_lenrek
810aed76a5 bcm: move CONFADDR parsing into bootargs.c, simplify initcode start() args handling 2019-04-11 19:10:47 +02:00
cinap_lenrek
6aff58df75 bcm: don't use PADDR() to convert bus address to physical in vcore 2019-04-11 17:12:20 +02:00
cinap_lenrek
9ae99fb5ad kernel: get rid of KSTKSIZE alias for KSTACK 2019-04-11 14:05:23 +02:00
cinap_lenrek
37d36fdd7f kernel: get rid of PTR2UINT() and UINT2PTR() macros 2019-04-11 13:51:38 +02:00
cinap_lenrek
753fa51b77 bcm: dont assume PHYSDRAM 0 in dmaaddr(), fix dmaioaddr() 2019-04-11 13:49:41 +02:00
cinap_lenrek
6a3a3d69c6 bcm: add pl011 uart driver
the raspi has two uarts, the pl011 and the mini. only one
can be used at a time due to pin muxing. the bcm kernel
uses the mini by default.
2019-04-11 13:21:06 +02:00
cinap_lenrek
fe34e52d19 bcm: move okay() from uartmini.c to devarch.c 2019-04-10 15:06:56 +02:00
cinap_lenrek
f00aa6b92a bcm: add irq.c to mkfile 2019-04-10 15:06:24 +02:00
cinap_lenrek
55a3964517 bcm: move interrupt handling out of trap.c into irq.c 2019-04-10 15:04:59 +02:00
cinap_lenrek
8b160d1ea1 bcm: remove obsolete TSTKTOP constant 2019-04-04 15:23:20 +02:00
cinap_lenrek
88ccea37f6 kernel: remove ptclbsum dependencies from configs 2019-02-27 08:47:17 +01:00
cinap_lenrek
242403d9f9 pi, pi2: remove ptclbsum dependency from config 2019-02-27 08:38:19 +01:00
cinap_lenrek
31637404ba bcm: include sdmmc in pi kernel configuration 2019-02-01 23:31:44 +01:00
cinap_lenrek
cefc849a95 devdraw: get rid of softscreen==0xa110c hack and make attachscreen() return Memdata*
all screen implementations use a Memimage* internally
for the framebuffer, so we can return a shared reference
to its Memdata structure in attachscreen() instead of
a framebuffer data pointer.

this eleminates the softscreen == 0xa110c hack as we
always use shared Memdata* now.
2019-01-30 18:22:52 +01:00
cinap_lenrek
8e1218aceb bcm: list devswap only once in devtab array 2019-01-30 18:05:04 +01:00
cinap_lenrek
85afec4c2f bcm: intrenable() can happen from any cpu in case of dma interrupts 2018-11-08 20:26:32 +01:00
cinap_lenrek
c0d21d35b1 bcm: cleanup timer code
- calculate hardcoded constants for more clarity
- avoid unneccesary modification of cntpns ctl register
- revert enabling IRQcntpns for cpu0
- remove unused Localintpending register offset constant
2018-11-07 17:02:09 +01:00
cinap_lenrek
385f52183c bcm: simplify irq handling by having per cpu Vctl chain 2018-11-07 16:49:50 +01:00
cinap_lenrek
b0d226705c bcm: speed up co-processor operations by avoiding i+d cache flush on each operation
coproc.c generated the instrucitons anew each time,
requiering a i+d cache flush for each operation.

instead, we can speed this up like this:

given that the coprocessor registers are per cpu, we can
assume that interrupts have already been disabled by
the caller to prevent a process switch to another cpu.

we cache the instructions generated in a static append
only buffer and maintain separate end pointers for each
cpu.

the cache flushes only need to be done when new
operations have been added to the buffer.
2018-11-07 16:48:14 +01:00
cinap_lenrek
89c659d80b bcm: fix mysterious core clock resets under SMP (thanks richard miller)
reference: https://github.com/raspberrypi/firmware/issues/542

procsave(Proc* p)
{
	uvlong t;

	cycles(&t);
	p->pcycles += t;

// TODO: save and restore VFPv3 FP state once 5[cal] know the new registers.
	fpuprocsave(p);
	/*
	 * Prevent the following scenario:
	 *	pX sleeps on cpuA, leaving its page tables in mmul1
	 *	pX wakes up on cpuB, and exits, freeing its page tables
	 *  pY on cpuB allocates a freed page table page and overwrites with data
	 *  cpuA takes an interrupt, and is now running with bad page tables
	 * In theory this shouldn't hurt because only user address space tables
	 * are affected, and mmuswitch will clear mmul1 before a user process is
	 * dispatched.  But empirically it correlates with weird problems, eg
	 * resetting of the core clock at 0x4000001C which confuses local timers.
	 */
	if(conf.nmach > 1)
		mmuswitch(nil);
}
2018-11-04 16:00:32 +01:00
cinap_lenrek
dd82b657c0 bcm: fix mistake in mkfile 2018-11-01 01:07:51 +01:00
cinap_lenrek
5608be398e bcm: fix /dev/reboot text/data corruption (thanks richard miller)
- clean dcache before turning off caches and mmu (rebootcode.s)
- use WFE and inter-core mailboxes for cpu startup (rebootcode.s)
- disable SMP during dcache invalidation before enabling caches and mmu (in armv7.s)
2018-10-31 19:48:16 +01:00
cinap_lenrek
8e9d2434e9 bcm: provide /dev/cputemp in a format stats can understand 2018-10-28 07:10:27 +01:00
cinap_lenrek
b715c39bfa bcm: simplify reboot code
- synchronize rebootcode installation
- handle the 1MB identity map in mmu.c (mmuinit1())
- do not overlap CONFADDR with rebootcode, the non boot
  processors are parked there.
- make REBOOTADDR physical address
2018-10-28 06:16:10 +01:00
cinap_lenrek
0fc2adb43d bcm: cleanup clock code
- disable local clock on interrupt to prevent accidents when reenabling
- always regitster local clock interrupt handler, even for cpu0
- simplify microdelay()
- don't mess with watchdog
2018-10-28 06:09:05 +01:00
cinap_lenrek
f17a5cc2cf bcm: fix l2 cache maintenance routines for raspi3 (armv8)
armv8 has 16-way l2, so adjust shift for the set-way cache
tag format.
2018-10-28 06:05:43 +01:00