bcm: simplify irq handling by having per cpu Vctl chain
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parent
b0d226705c
commit
385f52183c
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@ -13,7 +13,6 @@
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#include "arm.h"
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#define INTREGS (VIRTIO+0xB200)
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#define LOCALREGS (VIRTIO+IOSIZE)
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typedef struct Intregs Intregs;
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typedef struct Vctl Vctl;
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@ -51,7 +50,6 @@ struct Intregs {
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struct Vctl {
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Vctl *next;
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int irq;
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int cpu;
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u32int *reg;
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u32int mask;
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void (*f)(Ureg*, void*);
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@ -59,7 +57,7 @@ struct Vctl {
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};
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static Lock vctllock;
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static Vctl *vctl, *vfiq;
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static Vctl *vctl[MAXMACH], *vfiq;
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static char *trapnames[PsrMask+1] = {
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[ PsrMusr ] "user mode",
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@ -82,6 +80,7 @@ trapinit(void)
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{
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Vpage0 *vpage0;
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intrcpushutdown();
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if (m->machno == 0) {
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/* disable everything */
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intrsoff();
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@ -110,10 +109,10 @@ intrcpushutdown(void)
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if(soc.armlocal == 0)
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return;
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enable = (u32int*)(LOCALREGS + Localtimerint) + m->machno;
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enable = (u32int*)(ARMLOCAL + Localtimerint) + m->machno;
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*enable = 0;
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if(m->machno){
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enable = (u32int*)(LOCALREGS + Localmboxint) + m->machno;
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enable = (u32int*)(ARMLOCAL + Localmboxint) + m->machno;
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*enable = 1;
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}
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}
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@ -143,8 +142,8 @@ irq(Ureg* ureg)
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int clockintr;
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clockintr = 0;
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for(v = vctl; v; v = v->next)
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if(v->cpu == m->machno && (*v->reg & v->mask) != 0){
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for(v = vctl[m->machno]; v != nil; v = v->next)
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if((*v->reg & v->mask) != 0){
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coherence();
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v->f(ureg, v->a);
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coherence();
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@ -180,19 +179,16 @@ irqenable(int irq, void (*f)(Ureg*, void*), void* a)
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u32int *enable;
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ip = (Intregs*)INTREGS;
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v = (Vctl*)malloc(sizeof(Vctl));
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if(v == nil)
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if((v = xalloc(sizeof(Vctl))) == nil)
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panic("irqenable: no mem");
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v->irq = irq;
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v->cpu = 0;
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if(irq >= IRQlocal){
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v->reg = (u32int*)(LOCALREGS + Localintpending) + m->machno;
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v->reg = (u32int*)(ARMLOCAL + Localintpending) + m->machno;
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if(irq >= IRQmbox0)
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enable = (u32int*)(LOCALREGS + Localmboxint) + m->machno;
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enable = (u32int*)(ARMLOCAL + Localmboxint) + m->machno;
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else
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enable = (u32int*)(LOCALREGS + Localtimerint) + m->machno;
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enable = (u32int*)(ARMLOCAL + Localtimerint) + m->machno;
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v->mask = 1 << (irq - IRQlocal);
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v->cpu = m->machno;
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}else if(irq >= IRQbasic){
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enable = &ip->ARMenable;
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v->reg = &ip->ARMpending;
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@ -211,8 +207,8 @@ irqenable(int irq, void (*f)(Ureg*, void*), void* a)
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vfiq = v;
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ip->FIQctl = Fiqenable | irq;
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}else{
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v->next = vctl;
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vctl = v;
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v->next = vctl[m->machno];
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vctl[m->machno] = v;
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if(irq >= IRQmbox0){
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if(irq <= IRQmbox3)
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*enable |= 1 << (irq - IRQmbox0);
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