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bcm, bcm64: fix cache operations for dma and emmc

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always clean AND invalidate caches before dma read,
never just invalidate as the buffer might not be
aligned to cache lines...

we have to invalidate caches again *AFTER* the dma
read has completed. the processor can bring in data
speculatively into the cache while the dma in in
flight.
This commit is contained in:
cinap_lenrek 2019-05-19 16:54:50 +02:00
parent d667607c26
commit c881e33e8e
2 changed files with 4 additions and 2 deletions
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4
sys/src/9/bcm/dma.c
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@ -170,7 +170,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len)
ti = 0;
switch(dir){
case DmaD2M:
cachedinvse(dst, len);
cachedwbinvse(dst, len);
ti = Srcdreq | Destinc;
cb->sourcead = dmaioaddr(src);
cb->destad = dmaaddr(dst);
@ -183,7 +183,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len)
break;
case DmaM2M:
cachedwbse(src, len);
cachedinvse(dst, len);
cachedwbinvse(dst, len);
ti = Srcinc | Destinc;
cb->sourcead = dmaaddr(src);
cb->destad = dmaaddr(dst);

2
sys/src/9/bcm/emmc.c
View file

@ -398,6 +398,8 @@ emmcio(int write, uchar *buf, int len)
}
if(i)
WR(Interrupt, i);
if(!write)
cachedinvse(buf, len);
poperror();
okay(0);
}