bcm: fix l2 cache maintenance routines for raspi3 (armv8)
armv8 has 16-way l2, so adjust shift for the set-way cache tag format.
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1 changed files with 5 additions and 15 deletions
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@ -131,17 +131,6 @@ TEXT l2cacheuinv(SB), $-4
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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/*
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* these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
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* the Cortex-A8 L2 cache (A=3, L=6).
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* A = log2(# of ways), L = log2(bytes per cache line).
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* see armv7 arch ref p. 1403.
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*/
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#define L1WAYSH 30
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#define L1SETSH 6
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#define L2WAYSH 29
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#define L2SETSH 6
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/*
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* callers are assumed to be the above l1 and l2 ops.
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* R0 is the function to call in the innermost loop.
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@ -184,11 +173,12 @@ TEXT wholecache+0(SB), $-4
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ADD $1, R2 /* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
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/* precompute set/way shifts for inner loop */
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MOVW $6, R4
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CMP $0, R8 /* cache == 1? */
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MOVW.EQ $L1WAYSH, R3 /* yes */
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MOVW.EQ $L1SETSH, R4
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MOVW.NE $L2WAYSH, R3 /* no */
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MOVW.NE $L2SETSH, R4
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MOVW.EQ $30, R3 /* l1 */
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MOVW.NE $29, R3 /* l2 */
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CMP $16, R5 /* armv8 has 16-way l2, adjust shift */
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MOVW.EQ $28, R3
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/* iterate over ways */
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MOVW $0, R7 /* R7: way */
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