bcm: fix l2 cache maintenance routines for raspi3 (armv8)

armv8 has 16-way l2, so adjust shift for the set-way cache
tag format.
This commit is contained in:
cinap_lenrek 2018-10-28 06:05:43 +01:00
parent 2ee4c08974
commit f17a5cc2cf

View file

@ -131,17 +131,6 @@ TEXT l2cacheuinv(SB), $-4
BL wholecache(SB)
MOVW.P 8(R13), R15
/*
* these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
* the Cortex-A8 L2 cache (A=3, L=6).
* A = log2(# of ways), L = log2(bytes per cache line).
* see armv7 arch ref p. 1403.
*/
#define L1WAYSH 30
#define L1SETSH 6
#define L2WAYSH 29
#define L2SETSH 6
/*
* callers are assumed to be the above l1 and l2 ops.
* R0 is the function to call in the innermost loop.
@ -184,11 +173,12 @@ TEXT wholecache+0(SB), $-4
ADD $1, R2 /* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
/* precompute set/way shifts for inner loop */
MOVW $6, R4
CMP $0, R8 /* cache == 1? */
MOVW.EQ $L1WAYSH, R3 /* yes */
MOVW.EQ $L1SETSH, R4
MOVW.NE $L2WAYSH, R3 /* no */
MOVW.NE $L2SETSH, R4
MOVW.EQ $30, R3 /* l1 */
MOVW.NE $29, R3 /* l2 */
CMP $16, R5 /* armv8 has 16-way l2, adjust shift */
MOVW.EQ $28, R3
/* iterate over ways */
MOVW $0, R7 /* R7: way */