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bcm: move fiq saved pc adjust into lexception.s so it can be shared with arm64

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This commit is contained in:
cinap_lenrek 2019-05-03 22:02:07 +02:00
parent 3ca395a36c
commit eb4bd4aa3e
3 changed files with 3 additions and 3 deletions
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4
sys/src/9/bcm/irq.c
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@ -83,6 +83,7 @@ irq(Ureg* ureg)
Vctl *v;
int clockintr;
m->intr++;
clockintr = 0;
for(v = vctl[m->machno]; v != nil; v = v->next)
if((*v->reg & v->mask) != 0){
@ -103,11 +104,10 @@ fiq(Ureg *ureg)
{
Vctl *v;
m->intr++;
v = vfiq;
if(v == nil)
panic("cpu%d: unexpected item in bagging area", m->machno);
m->intr++;
ureg->pc -= 4;
coherence();
v->f(ureg, v->a);
coherence();

1
sys/src/9/bcm/lexception.s
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@ -187,6 +187,7 @@ TEXT _vfiq(SB), 1, $-4 /* FIQ */
MOVW $PsrMfiq, R8 /* trap type */
MOVW SPSR, R9 /* interrupted psr */
MOVW R14, R10 /* interrupted pc */
SUB $4, R10 /* ureg->pc -= 4 */
MOVM.DB.W [R8-R10], (R13) /* save in ureg */
MOVM.DB.S [R0-R14], (R13) /* save interrupted regs */
SUB $(15*4), R13

1
sys/src/9/bcm/trap.c
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@ -188,7 +188,6 @@ trap(Ureg *ureg)
break;
case PsrMirq:
clockintr = irq(ureg);
m->intr++;
break;
case PsrMabt: /* prefetch fault */
x = ifsrget();