bcm: fix /dev/reboot text/data corruption (thanks richard miller)
- clean dcache before turning off caches and mmu (rebootcode.s) - use WFE and inter-core mailboxes for cpu startup (rebootcode.s) - disable SMP during dcache invalidation before enabling caches and mmu (in armv7.s)
This commit is contained in:
cinap_lenrek
parent
913be4e74a
commit
5608be398e
5 changed files with 103 additions and 86 deletions
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@ -145,7 +145,6 @@ getncpus(void)
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{
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int n, max;
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char *p;
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n = 4;
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if(n > MAXMACH)
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n = MAXMACH;
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@ -46,34 +46,34 @@ TEXT armstart(SB), 1, $-4
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BARRIERS
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/*
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* turn SMP on
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* invalidate tlb
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* turn SMP off
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $CpACsmp, R1 /* turn SMP on */
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BIC $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/*
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* clear mach and page tables
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*/
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MOVW $PADDR(MACHADDR), R1
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MOVW $PADDR(KTZERO), R2
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MOVW $0, R0
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_ramZ:
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MOVW R0, (R1)
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ADD $4, R1
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CMP R1, R2
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BNE _ramZ
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BNE _ramZ
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/*
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* start stack at top of mach (physical addr)
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* set up page tables for kernel
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*/
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MOVW $PADDR(MACHADDR+MACHSIZE-4), R13
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MOVW $PADDR(L1), R0
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BL mmuinit(SB)
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BL mmuinvalidate(SB)
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/*
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* set up domain access control and page table base
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@ -93,6 +93,14 @@ _ramZ:
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BL l2cacheuinv(SB)
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BARRIERS
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/*
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* turn SMP on
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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/*
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* enable caches, mmu, and high vectors
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*/
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@ -133,12 +141,10 @@ TEXT cpureset(SB), 1, $-4
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reset:
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/*
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* load physical base for SB addressing while mmu is off
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* keep a handy zero in R0 until first function call
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*/
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MOVW $setR12(SB), R12
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SUB $KZERO, R12
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ADD $PHYSDRAM, R12
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MOVW $0, R0
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/*
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* SVC mode, interrupts disabled
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@ -156,15 +162,12 @@ reset:
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BARRIERS
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/*
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* turn SMP on
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* invalidate tlb
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* turn SMP off
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $CpACsmp, R1 /* turn SMP on */
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BIC $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/*
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* find Mach for this cpu
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@ -173,6 +176,8 @@ reset:
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AND $(MAXMACH-1), R2 /* mask out non-cpu-id bits */
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SLL $2, R2 /* convert to word index */
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MOVW $machaddr(SB), R0
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BIC $KSEGM, R0
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ORR $PHYSDRAM, R0
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ADD R2, R0 /* R0 = &machaddr[cpuid] */
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MOVW (R0), R0 /* R0 = machaddr[cpuid] */
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CMP $0, R0
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@ -184,6 +189,8 @@ reset:
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*/
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ADD $(MACHSIZE-4), R(MACH), R13
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BL mmuinvalidate(SB)
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/*
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* set up domain access control and page table base
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*/
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@ -202,6 +209,14 @@ reset:
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BL cacheiinv(SB)
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BARRIERS
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/*
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* turn SMP on
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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/*
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* enable caches, mmu, and high vectors
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*/
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@ -242,7 +242,7 @@ launchinit(void)
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}
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cachedwbse(machaddr, sizeof machaddr);
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if((mach = startcpus(conf.nmach)) < conf.nmach)
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print("only %d cpu%s started\n", mach, mach == 1? "" : "s");
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print("only %d cpu%s started\n", mach, mach == 1? "" : "s");
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}
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static void
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@ -551,10 +551,9 @@ confinit(void)
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}
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static void
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rebootjump(ulong entry, ulong code, ulong size)
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rebootjump(void *entry, void *code, ulong size)
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{
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static void (*f)(ulong, ulong, ulong);
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static Lock lk;
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void (*f)(void*, void*, ulong);
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intrsoff();
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intrcpushutdown();
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@ -562,17 +561,10 @@ rebootjump(ulong entry, ulong code, ulong size)
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/* redo identity map */
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mmuinit1(1);
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lock(&lk);
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if(f == nil){
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/* setup reboot trampoline function */
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f = (void*)REBOOTADDR;
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memmove(f, rebootcode, sizeof(rebootcode));
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cachedwbse(f, sizeof(rebootcode));
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}
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unlock(&lk);
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/* setup reboot trampoline function */
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f = (void*)REBOOTADDR;
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memmove(f, rebootcode, sizeof(rebootcode));
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cacheuwbinv();
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l2cacheuwbinv();
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(*f)(entry, code, size);
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@ -587,9 +579,9 @@ exit(int)
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{
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cpushutdown();
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splfhi();
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if(m->machno != 0)
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rebootjump(0, 0, 0);
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archreboot();
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if(m->machno == 0)
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archreboot();
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rebootjump(0, 0, 0);
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}
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/*
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@ -609,13 +601,13 @@ void
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reboot(void *entry, void *code, ulong size)
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{
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writeconf();
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if (m->machno != 0) {
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while(m->machno != 0){
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procwired(up, 0);
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sched();
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}
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cpushutdown();
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delay(1000);
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delay(2000);
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splfhi();
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@ -630,7 +622,7 @@ reboot(void *entry, void *code, ulong size)
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wdogoff();
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/* off we go - never to return */
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rebootjump(PADDR(entry), PADDR(code), size);
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rebootjump(entry, code, size);
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}
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void
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@ -70,8 +70,6 @@ LIB=\
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/$objtype/lib/libmp.a\
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/$objtype/lib/libc.a\
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9:V: $p$CONF s$p$CONF
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$p$CONF:DQ: $CONF.c $OBJ $LIB mkfile
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$CC $CFLAGS '-DKERNDATE='`{date -n} $CONF.c
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echo '# linking raw kernel' # H6: no headers, data segment aligned
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@ -123,8 +121,8 @@ init.h:D: ../port/initcode.c init9.s
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reboot.h:D: rebootcode.s arm.s arm.h mem.h
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$AS rebootcode.s
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# -lc is only for memmove. -T arg is REBOOTADDR
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$LD -l -s -T0x1c00 -R4 -o reboot.out rebootcode.$O -lc
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# -T arg is REBOOTADDR
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$LD -l -s -T0x1c00 -R4 -o reboot.out rebootcode.$O
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{echo 'uchar rebootcode[]={'
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xd -1x reboot.out |
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sed -e '1,2d' -e 's/^[0-9a-f]+ //' -e 's/ ([0-9a-f][0-9a-f])/0x\1,/g'
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@ -6,25 +6,46 @@
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#define WFI WORD $0xe320f003 /* wait for interrupt */
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#define WFE WORD $0xe320f002 /* wait for event */
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/*
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* Turn off MMU, then copy the new kernel to its correct location
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* in physical memory. Then jump to the start of the kernel.
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*/
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/* main(PADDR(entry), PADDR(code), size); */
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TEXT main(SB), 1, $-4
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MOVW $setR12(SB), R12
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/* copy in arguments before stack gets unmapped */
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MOVW R0, R8 /* entry point */
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MOVW p2+4(FP), R9 /* source */
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MOVW n+8(FP), R6 /* byte count */
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MOVW R0, entry+0(FP)
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CMP $0, R0
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BEQ shutdown
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/* SVC mode, interrupts disabled */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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MOVW entry+0(FP), R8
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MOVW code+4(FP), R9
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MOVW size+8(FP), R6
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/* turn caches off */
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/* round to words */
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BIC $3, R8
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BIC $3, R9
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ADD $3, R6
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BIC $3, R6
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memloop:
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MOVM.IA.W (R9), [R1]
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MOVM.IA.W [R1], (R8)
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SUB.S $4, R6
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BNE memloop
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shutdown:
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/* clean dcache using appropriate code for armv6 or armv7 */
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MRC CpSC, 0, R1, C(CpID), C(CpIDfeat), 7 /* Memory Model Feature Register 3 */
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TST $0xF, R1 /* hierarchical cache maintenance? */
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BNE l2wb
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DSB
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEall
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B l2wbx
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l2wb:
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BL cachedwb(SB)
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BL l2cacheuwb(SB)
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l2wbx:
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/* load entry before turning off mmu */
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MOVW entry+0(FP), R8
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/* disable caches */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCpredict), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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@ -39,42 +60,34 @@ TEXT main(SB), 1, $-4
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $CpCmmu, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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/* continue with reboot only on cpu0 */
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CPUID(R2)
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BEQ bootcpu
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/* other cpus wait for inter processor interrupt from cpu0 */
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/* turn icache back on */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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ORR $(CpCicache), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/* turn SMP off */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BIC $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ISB
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DSB
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/* have entry? */
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CMP $0, R8
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BNE bootcpu
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/* other cpus wait for inter processor interrupt */
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CPUID(R2)
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dowfi:
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WFI
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MOVW $0x40000060, R1
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ADD R2<<2, R1
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MOVW 0(R1), R0
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AND $0x10, R0
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BEQ dowfi
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MOVW $0x8000, R1
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BL (R1)
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B dowfi
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WFE /* wait for event signal */
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MOVW $0x400000CC, R1 /* inter-core .startcpu mailboxes */
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ADD R2<<4, R1 /* mailbox for this core */
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MOVW 0(R1), R8 /* content of mailbox */
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CMP $0, R8
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BEQ dowfi /* if zero, wait again */
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bootcpu:
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/* set up a tiny stack for local vars and memmove args */
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MOVW R8, SP /* stack top just before kernel dest */
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SUB $20, SP /* allocate stack frame */
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BIC $KSEGM, R8 /* entry to physical */
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ORR $PHYSDRAM, R8
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BL (R8)
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B dowfi
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/* copy the kernel to final destination */
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MOVW R8, 16(SP) /* save dest (entry point) */
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MOVW R8, R0 /* first arg is dest */
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MOVW R9, 8(SP) /* push src */
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MOVW R6, 12(SP) /* push size */
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BL memmove(SB)
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MOVW 16(SP), R8 /* restore entry point */
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/* jump to kernel physical entry point */
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ORR R8,R8
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B (R8)
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B 0(PC)
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#define ICACHELINESZ 32
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#include "cache.v7.s"
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