reactos/hal/halx86/include/halp.h

612 lines
9.7 KiB
C
Raw Normal View History

/*
*
*/
#pragma once
#ifdef CONFIG_SMP
#define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
#else
#define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
#endif
/* Don't include this in freeloader */
#ifndef _BLDR_
extern KIRQL HalpIrqlSynchLevel;
#undef SYNCH_LEVEL
#define SYNCH_LEVEL HalpIrqlSynchLevel
#endif
typedef struct _HAL_BIOS_FRAME
{
ULONG SegSs;
ULONG Esp;
ULONG EFlags;
ULONG SegCs;
ULONG Eip;
PKTRAP_FRAME TrapFrame;
ULONG CsLimit;
ULONG CsBase;
ULONG CsFlags;
ULONG SsLimit;
ULONG SsBase;
ULONG SsFlags;
ULONG Prefix;
} HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
typedef
VOID
(__cdecl *PHAL_SW_INTERRUPT_HANDLER)(
VOID
);
typedef
VOID
(FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
IN PKTRAP_FRAME TrapFrame
);
#define HAL_APC_REQUEST 0
#define HAL_DPC_REQUEST 1
/* HAL profiling offsets in KeGetPcr()->HalReserved[] */
#define HAL_PROFILING_INTERVAL 0
#define HAL_PROFILING_MULTIPLIER 1
/* Usage flags */
#define IDT_REGISTERED 0x01
#define IDT_LATCHED 0x02
#define IDT_READ_ONLY 0x04
#define IDT_INTERNAL 0x11
#define IDT_DEVICE 0x21
#ifdef _M_AMD64
#define HALP_LOW_STUB_SIZE_IN_PAGES 5
#else
#define HALP_LOW_STUB_SIZE_IN_PAGES 3
#endif
- Cleanup HAL initialization code: - Initailize the clock increment separately from the calibration of stall execution. - Raise IRQL to the current IRQL (basically a no-op) to force a standard PIC state. Will be needed for the new IRQ implementation when it'll work. - Scan commandline for PCILOCK and BREAK parameters during hal initalization. The former is not supported, only saved, while the latter causes a breakpoint just like the windows implemetnation. - Get the bus type (ISA, EISA, MCA) on startup to support bootup from NTLDR. - Validate HAL to match the kernel (checked kernel and UP kernel). Also make the kernel set the proper PRCB flags for this. - Initialize the CMOS lock. - Setup HAL Dispatch table and enable call to HalQuerySystemInformation in the kernel since it now works. - Rewrite bus functions to get rid of the idea of "Bus handlers". This is a deprecated NT4 concept that ReactOS copied and only slows down performance. - Support custom private dispatch table PCI functions. - Provide default PCI functions. - Rewrite PCI functions using clean structures and code instead of magic macros and undocumented magic values. Use simple macros to generate PCI bus operations for write/read uchar, ushort and ulong. - Simplify function definitions for CMOS access. - Unify some dupli/tripi-cated code. - Fix definition of HaliSetSystemInformation. - Fix definitions of Bus Handler functions (add NTAPI). - Add official BUS_HANDLER definition to NDK. - Fix definition of HAL_PRIVATE_DISPATCH. - Remove some derecated code (isa.c and mca.c). svn path=/trunk/; revision=24872
2006-11-27 19:26:31 +00:00
/* Conversion functions */
#define BCD_INT(bcd) \
(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
#define INT_BCD(int) \
(UCHAR)(((int / 10) << 4) + (int % 10))
typedef
BOOLEAN
(NTAPI *PHAL_DISMISS_INTERRUPT)(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
HalpDismissIrqGeneric(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
HalpDismissIrq15(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
HalpDismissIrq13(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
HalpDismissIrq07(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
BOOLEAN
NTAPI
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
HalpDismissIrqLevel(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
HalpDismissIrq15Level(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
HalpDismissIrq13Level(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
BOOLEAN
NTAPI
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
HalpDismissIrq07Level(
IN KIRQL Irql,
IN ULONG Irq,
OUT PKIRQL OldIrql
);
VOID
__cdecl
[HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. [HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead. [NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C. [PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization. [PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling. svn path=/trunk/; revision=45320
2010-01-29 21:10:33 +00:00
HalpHardwareInterruptLevel(
VOID
);
//
// Hack Flags
//
#define HALP_REVISION_FROM_HACK_FLAGS(x) ((x) >> 24)
#define HALP_REVISION_HACK_FLAGS(x) ((x) >> 12)
#define HALP_HACK_FLAGS(x) ((x) & 0xFFF)
//
// Feature flags
//
#define HALP_CARD_FEATURE_FULL_DECODE 0x0001
//
// Match Flags
//
#define HALP_CHECK_CARD_REVISION_ID 0x10000
#define HALP_CHECK_CARD_SUBVENDOR_ID 0x20000
#define HALP_CHECK_CARD_SUBSYSTEM_ID 0x40000
//
// Mm PTE/PDE to Hal PTE/PDE
//
#define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
#define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
typedef struct _IDTUsageFlags
{
UCHAR Flags;
} IDTUsageFlags;
typedef struct
{
KIRQL Irql;
UCHAR BusReleativeVector;
} IDTUsage;
typedef struct _HalAddressUsage
{
struct _HalAddressUsage *Next;
CM_RESOURCE_TYPE Type;
UCHAR Flags;
struct
{
ULONG Start;
ULONG Length;
} Element[];
} ADDRESS_USAGE, *PADDRESS_USAGE;
/* adapter.c */
PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
/* sysinfo.c */
CODE_SEG("INIT")
VOID
NTAPI
HalpRegisterVector(IN UCHAR Flags,
IN ULONG BusVector,
IN ULONG SystemVector,
IN KIRQL Irql);
CODE_SEG("INIT")
VOID
NTAPI
HalpEnableInterruptHandler(IN UCHAR Flags,
IN ULONG BusVector,
IN ULONG SystemVector,
IN KIRQL Irql,
IN PVOID Handler,
IN KINTERRUPT_MODE Mode);
/* pic.c */
VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
VOID __cdecl HalpApcInterrupt(VOID);
VOID __cdecl HalpDispatchInterrupt(VOID);
PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2(VOID);
DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
/* profil.c */
extern BOOLEAN HalpProfilingStopped;
/* timer.c */
CODE_SEG("INIT") VOID NTAPI HalpInitializeClock(VOID);
VOID __cdecl HalpClockInterrupt(VOID);
VOID __cdecl HalpClockIpi(VOID);
VOID __cdecl HalpProfileInterrupt(VOID);
- Cleanup HAL initialization code: - Initailize the clock increment separately from the calibration of stall execution. - Raise IRQL to the current IRQL (basically a no-op) to force a standard PIC state. Will be needed for the new IRQ implementation when it'll work. - Scan commandline for PCILOCK and BREAK parameters during hal initalization. The former is not supported, only saved, while the latter causes a breakpoint just like the windows implemetnation. - Get the bus type (ISA, EISA, MCA) on startup to support bootup from NTLDR. - Validate HAL to match the kernel (checked kernel and UP kernel). Also make the kernel set the proper PRCB flags for this. - Initialize the CMOS lock. - Setup HAL Dispatch table and enable call to HalQuerySystemInformation in the kernel since it now works. - Rewrite bus functions to get rid of the idea of "Bus handlers". This is a deprecated NT4 concept that ReactOS copied and only slows down performance. - Support custom private dispatch table PCI functions. - Provide default PCI functions. - Rewrite PCI functions using clean structures and code instead of magic macros and undocumented magic values. Use simple macros to generate PCI bus operations for write/read uchar, ushort and ulong. - Simplify function definitions for CMOS access. - Unify some dupli/tripi-cated code. - Fix definition of HaliSetSystemInformation. - Fix definitions of Bus Handler functions (add NTAPI). - Add official BUS_HANDLER definition to NDK. - Fix definition of HAL_PRIVATE_DISPATCH. - Remove some derecated code (isa.c and mca.c). svn path=/trunk/; revision=24872
2006-11-27 19:26:31 +00:00
typedef struct _HALP_ROLLOVER
{
ULONG RollOver;
ULONG Increment;
} HALP_ROLLOVER, *PHALP_ROLLOVER;
VOID
NTAPI
HalpCalibrateStallExecution(VOID);
/* pci.c */
VOID HalpInitPciBus (VOID);
/* dma.c */
CODE_SEG("INIT") VOID HalpInitDma (VOID);
/* Non-generic initialization */
VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
VOID HalpInitPhase1(VOID);
VOID
NTAPI
HalpFlushTLB(VOID);
//
// KD Support
//
VOID
NTAPI
HalpCheckPowerButton(
VOID
);
CODE_SEG("INIT")
VOID
NTAPI
HalpRegisterKdSupportFunctions(
VOID
);
CODE_SEG("INIT")
NTSTATUS
NTAPI
HalpSetupPciDeviceForDebugging(
IN PVOID LoaderBlock,
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
);
CODE_SEG("INIT")
NTSTATUS
NTAPI
HalpReleasePciDeviceForDebugging(
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
);
//
// Memory routines
//
ULONG64
NTAPI
HalpAllocPhysicalMemory(
IN PLOADER_PARAMETER_BLOCK LoaderBlock,
IN ULONG64 MaxAddress,
IN PFN_NUMBER PageCount,
IN BOOLEAN Aligned
);
PVOID
NTAPI
HalpMapPhysicalMemory64Vista(
IN PHYSICAL_ADDRESS PhysicalAddress,
IN PFN_COUNT PageCount,
IN BOOLEAN FlushCurrentTLB
);
VOID
NTAPI
HalpUnmapVirtualAddressVista(
IN PVOID VirtualAddress,
IN PFN_COUNT NumberPages,
IN BOOLEAN FlushCurrentTLB
);
PVOID
NTAPI
HalpMapPhysicalMemory64(
IN PHYSICAL_ADDRESS PhysicalAddress,
IN PFN_COUNT PageCount
);
VOID
NTAPI
HalpUnmapVirtualAddress(
IN PVOID VirtualAddress,
IN PFN_COUNT NumberPages
);
/* sysinfo.c */
NTSTATUS
NTAPI
HaliHandlePCIConfigSpaceAccess(
_In_ BOOLEAN IsRead,
_In_ ULONG Port,
_In_ ULONG Length,
_Inout_ PULONG Buffer
);
- Cleanup HAL initialization code: - Initailize the clock increment separately from the calibration of stall execution. - Raise IRQL to the current IRQL (basically a no-op) to force a standard PIC state. Will be needed for the new IRQ implementation when it'll work. - Scan commandline for PCILOCK and BREAK parameters during hal initalization. The former is not supported, only saved, while the latter causes a breakpoint just like the windows implemetnation. - Get the bus type (ISA, EISA, MCA) on startup to support bootup from NTLDR. - Validate HAL to match the kernel (checked kernel and UP kernel). Also make the kernel set the proper PRCB flags for this. - Initialize the CMOS lock. - Setup HAL Dispatch table and enable call to HalQuerySystemInformation in the kernel since it now works. - Rewrite bus functions to get rid of the idea of "Bus handlers". This is a deprecated NT4 concept that ReactOS copied and only slows down performance. - Support custom private dispatch table PCI functions. - Provide default PCI functions. - Rewrite PCI functions using clean structures and code instead of magic macros and undocumented magic values. Use simple macros to generate PCI bus operations for write/read uchar, ushort and ulong. - Simplify function definitions for CMOS access. - Unify some dupli/tripi-cated code. - Fix definition of HaliSetSystemInformation. - Fix definitions of Bus Handler functions (add NTAPI). - Add official BUS_HANDLER definition to NDK. - Fix definition of HAL_PRIVATE_DISPATCH. - Remove some derecated code (isa.c and mca.c). svn path=/trunk/; revision=24872
2006-11-27 19:26:31 +00:00
NTSTATUS
NTAPI
HaliQuerySystemInformation(
IN HAL_QUERY_INFORMATION_CLASS InformationClass,
IN ULONG BufferSize,
IN OUT PVOID Buffer,
OUT PULONG ReturnedLength
);
NTSTATUS
NTAPI
HaliSetSystemInformation(
IN HAL_SET_INFORMATION_CLASS InformationClass,
IN ULONG BufferSize,
IN OUT PVOID Buffer
);
//
// BIOS Routines
//
BOOLEAN
NTAPI
HalpBiosDisplayReset(
VOID
);
VOID
FASTCALL
HalpExitToV86(
PKTRAP_FRAME TrapFrame
);
VOID
__cdecl
HalpRealModeStart(
VOID
);
- Stub out DbgKdWriteVirtualMemoryApi, DbgKdReadPhysicalMemoryApi, DbgKdWritePhysicalMemoryApi, DbgKdWriteBreakPointExApi, DbgKdRestoreBreakPointExApi, DbgKdSearchMemoryApi and DbgKdFillMemoryApi cases more properly. - Fail on physical memory write like we do for read too. - Don't handle OldVlm1/2 as they appear to be deprecated and unhandled in Windows. - Implement HalHaltSystem to halt execution in a portable way. Default to xHalHaltSystem, a simple infinite loop, if we get called before HAL has initialized. Use this in KiBugCheckDebugBreak and the system shutdown handler instead of x86/AMD64/ARM intrinsics. - Don't try to halt the CPU if KeBugCheck has been called 3 times or more -- if this happens, something has gone very wrong, and we shouldn't try to do anything special. Just loop infinitely. - Fix KiBugCheckDebugBreak -- it shouldn't halt execution when called for the first chance as bugcheck callbacks have not been invoked at this point (nor has the BSOD been displayed). Use SEH to protect against a crash instead of checking KdDebuggerNotPresent as the debugger, if it is present, *could* disconnect while the trap is being handled. Also, don't halt execution if the debugger handled the breakpoint, just break again. - Don't call MmMapIoSpace from HalpReboot! The reboot might take place at elevated IRQL (as high as HIGH_LEVEL if called from KeBugCheck), and thus can't use any Mm support routines. Use a PTE from the reserved HAL region and map it ourselves instead as done in the BIOS call code. - Acquire the display ownership in HalReturnToFirmware in case the caller hasn't done so (as done in the KD reboot routine, for example). - Just include ntndk.h in hal.h instead of including 6 NDK headers (which turns into more than half of the NDK anyway since those headers include other NDK headers). - Crashing and rebooting from KD now works properly. svn path=/trunk/; revision=43380
2009-10-11 20:16:45 +00:00
//
// Processor Halt Routine
//
VOID
NTAPI
HaliHaltSystem(
VOID
);
//
// CMOS Routines
//
CODE_SEG("INIT")
VOID
NTAPI
HalpInitializeCmos(
VOID
);
_Requires_lock_held_(HalpSystemHardwareLock)
UCHAR
NTAPI
HalpReadCmos(
IN UCHAR Reg
);
_Requires_lock_held_(HalpSystemHardwareLock)
VOID
NTAPI
HalpWriteCmos(
IN UCHAR Reg,
IN UCHAR Value
);
//
// Spinlock for protecting CMOS access
//
_Acquires_lock_(HalpSystemHardwareLock)
VOID
NTAPI
HalpAcquireCmosSpinLock(
VOID
);
_Releases_lock_(HalpSystemHardwareLock)
VOID
NTAPI
HalpReleaseCmosSpinLock(
VOID
);
VOID
NTAPI
HalpInitializeLegacyPICs(
VOID
);
NTSTATUS
NTAPI
HalpOpenRegistryKey(
IN PHANDLE KeyHandle,
IN HANDLE RootKey,
IN PUNICODE_STRING KeyName,
IN ACCESS_MASK DesiredAccess,
IN BOOLEAN Create
);
CODE_SEG("INIT")
VOID
NTAPI
HalpGetNMICrashFlag(
VOID
);
CODE_SEG("INIT")
BOOLEAN
NTAPI
HalpGetDebugPortTable(
VOID
);
CODE_SEG("INIT")
VOID
NTAPI
HalpReportSerialNumber(
VOID
);
CODE_SEG("INIT")
NTSTATUS
NTAPI
HalpMarkAcpiHal(
VOID
);
CODE_SEG("INIT")
VOID
NTAPI
HalpBuildAddressMap(
VOID
);
CODE_SEG("INIT")
VOID
NTAPI
HalpReportResourceUsage(
IN PUNICODE_STRING HalName,
IN INTERFACE_TYPE InterfaceType
);
CODE_SEG("INIT")
ULONG
NTAPI
HalpIs16BitPortDecodeSupported(
VOID
);
NTSTATUS
NTAPI
HalpQueryAcpiResourceRequirements(
OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
);
VOID
FASTCALL
KeUpdateSystemTime(
IN PKTRAP_FRAME TrapFrame,
IN ULONG Increment,
IN KIRQL OldIrql
);
VOID
NTAPI
KeUpdateRunTime(
_In_ PKTRAP_FRAME TrapFrame,
_In_ KIRQL Irql);
CODE_SEG("INIT")
[HAL]: Bus support in the HAL actually creates a further wedge between the different x86 HALs: There are actually two dinstinct implementations. On the ACPI HAL, the system is assumed not to have things like special ISA, MCA, EISA buses, and a PCI driver is used in combination with the ACPI Interface for PCI Bus support. On non-ACPI systems, the legacy "Bus Handler" library is used, and the HAL provides a core set of CMOS, EISA, ISA, MCA and PCI bus handlers, each with their own routines and specific code. Additionally, PCI IRQ Routing and other PCI bus internals are handled directly by the HAL -- on the ACPI HAL, the PCI Bus support is implemented through a "Fake"/static bus handler, just to keep the functions shared. On ReactOS, both the ACPI and non-ACPI HAL were currently using a mix of both HAL bus handling types, mostly implemented the "ACPI way" (with a fake PCI bus handler and such). As a result, none of the Hal*Bus HALDISPATCH routines were implemented, which bus drivers expect to find when they're not on ACPI systems (ReactOS today). eVb's new PCI driver was crashing, for example. Furthermore, legacy systems suffer, because the ACPI HAL Bus routines (that we currently have) expect perfect ACPI-style-compliant systems, not the legacy crap from the early 90ies. This works fine in VMs and new hardware, but old hardware is left behind. This patch basically corrects the first part of the problem, by making the bus handling support separate between ACPI and non-ACPI HALs. For now, the code remains 100% the same in functionality between both. However, I have started adding the first few elements: [HAL]: Implement HalRegisterBusHandler HALDISPATCH routine. [HAL]: On legacy HALs, register the CMOS, ISA, SYSTEM handlers. [HAL]: Add cmosbus.c. Stub all bus-specific bus handler routines in the xxxbus.c files. No real functionality change occurs with this patch, yet. svn path=/trunk/; revision=47649
2010-06-07 01:09:41 +00:00
VOID
NTAPI
HalpInitBusHandlers(
VOID
);
NTSTATUS
NTAPI
HaliInitPnpDriver(
VOID
);
CODE_SEG("INIT")
VOID
NTAPI
HalpDebugPciDumpBus(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER PciSlot,
IN ULONG i,
IN ULONG j,
IN ULONG k,
IN PPCI_COMMON_CONFIG PciData
);
VOID
NTAPI
HalpInitProcessor(
IN ULONG ProcessorNumber,
IN PLOADER_PARAMETER_BLOCK LoaderBlock
);
#if defined(SARCH_PC98)
BOOLEAN
NTAPI
HalpDismissIrq08(
_In_ KIRQL Irql,
_In_ ULONG Irq,
_Out_ PKIRQL OldIrql
);
BOOLEAN
NTAPI
HalpDismissIrq08Level(
_In_ KIRQL Irql,
_In_ ULONG Irq,
_Out_ PKIRQL OldIrql
);
VOID
NTAPI
HalpInitializeClockPc98(VOID);
extern ULONG PIT_FREQUENCY;
#endif /* SARCH_PC98 */
VOID
NTAPI
HalInitializeBios(
_In_ ULONG Phase,
_In_ PLOADER_PARAMETER_BLOCK LoaderBlock
);
#ifdef _M_AMD64
#define KfLowerIrql KeLowerIrql
#define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
#endif // _M_AMD64
extern BOOLEAN HalpNMIInProgress;
extern ADDRESS_USAGE HalpDefaultIoSpace;
- Cleanup HAL initialization code: - Initailize the clock increment separately from the calibration of stall execution. - Raise IRQL to the current IRQL (basically a no-op) to force a standard PIC state. Will be needed for the new IRQ implementation when it'll work. - Scan commandline for PCILOCK and BREAK parameters during hal initalization. The former is not supported, only saved, while the latter causes a breakpoint just like the windows implemetnation. - Get the bus type (ISA, EISA, MCA) on startup to support bootup from NTLDR. - Validate HAL to match the kernel (checked kernel and UP kernel). Also make the kernel set the proper PRCB flags for this. - Initialize the CMOS lock. - Setup HAL Dispatch table and enable call to HalQuerySystemInformation in the kernel since it now works. - Rewrite bus functions to get rid of the idea of "Bus handlers". This is a deprecated NT4 concept that ReactOS copied and only slows down performance. - Support custom private dispatch table PCI functions. - Provide default PCI functions. - Rewrite PCI functions using clean structures and code instead of magic macros and undocumented magic values. Use simple macros to generate PCI bus operations for write/read uchar, ushort and ulong. - Simplify function definitions for CMOS access. - Unify some dupli/tripi-cated code. - Fix definition of HaliSetSystemInformation. - Fix definitions of Bus Handler functions (add NTAPI). - Add official BUS_HANDLER definition to NDK. - Fix definition of HAL_PRIVATE_DISPATCH. - Remove some derecated code (isa.c and mca.c). svn path=/trunk/; revision=24872
2006-11-27 19:26:31 +00:00
extern KSPIN_LOCK HalpSystemHardwareLock;
extern PADDRESS_USAGE HalpAddressUsageList;
extern LARGE_INTEGER HalpPerfCounter;
extern KAFFINITY HalpActiveProcessors;
extern BOOLEAN HalDisableFirmwareMapper;
extern PWCHAR HalHardwareIdString;
extern PWCHAR HalName;
extern KAFFINITY HalpDefaultInterruptAffinity;
extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
extern const USHORT HalpBuildType;