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[HAL]: Implement and document the HalpSpecialDismissTable. Explain how each IRQ should be handled and what the special cases are. Implement said special cases (based on ISA System Architecture, 3rd Edition).
[HAL]: Implement HalBeginSystemInterrupt in C instead of ASM, it jumps into one of the IRQ handlers registered in the HalpSpecialDismissTable. svn path=/trunk/; revision=45237
This commit is contained in:
Sir Richard
parent
f79bc2e7f0
commit
1215f71ed8
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@ -84,38 +84,6 @@ FindHigherIrqlMask:
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.long 0 /* IRQL 30 */
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.long 0 /* IRQL 31 */
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HalpSpecialDismissTable:
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.rept 7
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.long GenericIRQ /* IRQ 0-7 */
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.endr
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.long IRQ7 /* IRQ 7 */
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.rept 5
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.long GenericIRQ /* IRQ 8-12 */
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.endr
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.long IRQ13 /* IRQ 13 */
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.long GenericIRQ /* IRQ 14 */
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.long IRQ15 /* IRQ 15 */
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.rept 20
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.long GenericIRQ /* IRQ 16-35 */
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.endr
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#if DBG
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.rept 172
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.long InvalidIRQ /* IRQ 36-207 */
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.endr
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#endif
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HalpSpecialDismissLevelTable:
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.rept 7
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.long GenericIRQLevel /* IRQ 0-7 */
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.endr
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.long IRQ7Level /* IRQ 7 */
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.rept 5
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.long GenericIRQLevel /* IRQ 8-12 */
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.endr
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.long IRQ13Level /* IRQ 13 */
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.long GenericIRQLevel /* IRQ 14 */
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.long IRQ15Level /* IRQ 15 */
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SWInterruptLookUpTable:
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.byte PASSIVE_LEVEL /* IRR 0 */
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.byte PASSIVE_LEVEL /* IRR 1 */
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@ -210,198 +178,6 @@ AfterCall:
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ret
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.endfunc
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.globl _HalBeginSystemInterrupt@12
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.func HalBeginSystemInterrupt@12
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_HalBeginSystemInterrupt@12:
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/* Convert to IRQ and call the handler */
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xor ecx, ecx
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mov cl, byte ptr [esp+8]
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sub ecx, PRIMARY_VECTOR_BASE
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jmp HalpSpecialDismissTable[ecx*4]
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IRQ15:
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/* This is IRQ 15, check if it's spurious */
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mov al, 0xB
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out 0xA0, al
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jmp $+2
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in al, 0xA0
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test al, 0x80
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jnz GenericIRQ
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/* Cascaded interrupt... dismiss it and return FALSE */
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CascadedInterrupt:
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mov al, 0x62
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out 0x20, al
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mov eax, 0
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ret 12
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IRQ7:
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/* This is IRQ 7, check if it's spurious */
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mov al, 0xB
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out 0x20, al
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jmp $+2
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in al, 0x20
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test al, 0x80
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jnz GenericIRQ
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/* It is, return FALSE */
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mov eax, 0
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ret 12
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IRQ13:
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/* AT 80287 latch clear */
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xor al, al
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out 0xF0, al
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GenericIRQ:
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/* Get current and new IRQL */
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xor eax, eax
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mov al, byte ptr [esp+4]
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mov ebx, PCR[KPCR_IRQL]
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/* Set and save old */
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mov PCR[KPCR_IRQL], eax
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mov edx, [esp+12]
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mov [edx], bl
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/* Set IRQ mask in the PIC */
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mov eax, KiI8259MaskTable[eax*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Check to which PIC the EOI was sent */
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mov eax, ecx
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cmp eax, 8
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jnb Pic1
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Pic1:
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/* Write mask to slave PIC */
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mov al, 0x20
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out 0xA0, al
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mov al, 0x62
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out 0x20, al
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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#if DBG
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InvalidIRQ:
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/* Dismiss it */
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mov eax, 0
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ret 12
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#endif
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.endfunc
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IRQ15Level:
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/* This is IRQ 15, check if it's spurious */
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mov al, 0xB
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out 0xA0, al
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jmp $+2
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in al, 0xA0
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test al, 0x80
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jnz GenericIRQLevel
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jmp CascadedInterrupt
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IRQ7Level:
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/* This is IRQ 7, check if it's spurious */
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mov al, 0xB
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out 0x20, al
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jmp $+2
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in al, 0x20
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test al, 0x80
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jnz GenericIRQLevel
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/* It is, return FALSE */
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SpuriousInterrupt:
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mov eax, 0
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ret 12
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IRQ13Level:
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/* AT 80287 latch clear */
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xor al, al
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out 0xF0, al
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GenericIRQLevel:
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/* Save IRQL */
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xor eax, eax
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mov al, [esp+4]
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/* Set IRQ mask in the PIC */
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mov eax, KiI8259MaskTable[eax*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Compute new IRR */
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mov eax, ecx
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mov ebx, 1
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add ecx, 4
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shl ebx, cl
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or PCR[KPCR_IRR], ebx
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/* Get IRQLs */
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mov cl, [esp+4]
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mov bl, PCR[KPCR_IRQL]
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mov edx, [esp+12]
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/* Check to which PIC the EOI was sent */
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cmp eax, 8
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jnb Pic1Level
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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/* Check for spurious */
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cmp cl, bl
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jbe SpuriousInterrupt
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/* Write IRQL values */
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movzx ecx, cl
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mov PCR[KPCR_IRQL], ecx
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mov [edx], bl
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Pic1Level:
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/* Write mask to slave and master PIC */
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add al, 0x58
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out 0xA0, al
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mov al, 0x62
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out 0x20, al
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/* Was this a lower interrupt? */
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cmp cl, bl
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jbe SpuriousInterrupt
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/* Write IRQL values */
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movzx ecx, cl
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mov PCR[KPCR_IRQL], ecx
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mov [edx], bl
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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.globl _HalEndSystemInterrupt@8
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.func HalEndSystemInterrupt@8
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_HalEndSystemInterrupt@8:
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@ -14,6 +14,58 @@
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/* GLOBALS ********************************************************************/
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/*
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* This table basically keeps track of level vs edge triggered interrupts.
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* Windows has 250+ entries, but it seems stupid to replicate that since the PIC
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* can't actually have that many.
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*
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* When a level interrupt is registered, the respective pointer in this table is
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* modified to point to a dimiss routine for level interrupts instead.
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*
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* The other thing this table does is special case IRQ7, IRQ13 and IRQ15:
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*
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* - If an IRQ line is deasserted before it is acknowledged due to a noise spike
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* generated by an expansion device (since the IRQ line is low during the 1st
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* acknowledge bus cycle), the i8259 will keep the line low for at least 100ns
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* When the spike passes, a pull-up resistor will return the IRQ line to high.
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* Since the PIC requires the input be high until the first acknowledge, the
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* i8259 knows that this was a spurious interrupt, and on the second interrupt
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* acknowledge cycle, it reports this to the CPU. Since no valid interrupt has
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* actually happened Intel hardcoded the chip to report IRQ7 on the master PIC
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* and IRQ15 on the slave PIC (IR7 either way).
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*
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* "ISA System Architecture", 3rd Edition, states that these cases should be
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* handled by reading the respective Interrupt Service Request (ISR) bits from
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* the affected PIC, and validate whether or not IR7 is set. If it isn't, then
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* the interrupt is spurious and should be ignored.
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*
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* Note that for a spurious IRQ15, we DO have to send an EOI to the master for
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* IRQ2 since the line was asserted by the slave when it received the spurious
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* IRQ15!
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*
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* - When the 80287/80387 math co-processor generates an FPU/NPX trap, this is
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* connected to IRQ13, so we have to clear the busy latch on the NPX port.
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*/
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PHAL_DISMISS_INTERRUPT HalpSpecialDismissTable[16] =
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{
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrq07,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrq13,
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HalpDismissIrqGeneric,
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HalpDismissIrq15
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};
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/* This table contains the static x86 PIC mapping between IRQLs and IRQs */
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ULONG KiI8259MaskTable[32] =
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{
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@ -342,6 +394,139 @@ HalClearSoftwareInterrupt(IN KIRQL Irql)
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KeGetPcr()->IRR &= ~(1 << Irql);
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}
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/* INTERRUPT DISMISSAL FUNCTIONS **********************************************/
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BOOLEAN
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FORCEINLINE
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_HalpDismissIrqGeneric(IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql)
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{
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PIC_MASK Mask;
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KIRQL CurrentIrql;
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I8259_OCW2 Ocw2;
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PKPCR Pcr = KeGetPcr();
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/* First save current IRQL and compare it to the requested one */
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CurrentIrql = Pcr->Irql;
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/* Set the new IRQL and return the current one */
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Pcr->Irql = Irql;
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*OldIrql = CurrentIrql;
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/* Set new PIC mask */
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Mask.Both = KiI8259MaskTable[Irql] | Pcr->IDR;
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__outbyte(PIC1_DATA_PORT, Mask.Master);
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__outbyte(PIC2_DATA_PORT, Mask.Slave);
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/* Prepare OCW2 for EOI */
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Ocw2.Bits = 0;
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Ocw2.EoiMode = SpecificEoi;
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/* Check which PIC needs the EOI */
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if (Irq > 8)
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{
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/* Send the EOI for the IRQ */
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__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | (Irq - 8));
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/* Send the EOI for IRQ2 on the master because this was cascaded */
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__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
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}
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else
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{
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/* Send the EOI for the IRQ */
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__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | Irq);
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}
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/* Enable interrupts and return success */
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_enable();
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return TRUE;
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}
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrqGeneric(IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql)
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{
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/* Run the inline code */
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return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
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}
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq15(IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql)
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{
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I8259_OCW3 Ocw3;
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I8259_OCW2 Ocw2;
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I8259_ISR Isr;
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/* Request the ISR */
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Ocw3.Bits = 0;
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Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
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Ocw3.ReadRequest = ReadIsr;
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__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
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/* Read the ISR */
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Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
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/* Is IRQ15 really active (this is IR7) */
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if (Isr.Irq7 == FALSE)
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{
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/* It isn't, so we have to EOI IRQ2 because this was cascaded */
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Ocw2.Bits = 0;
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Ocw2.EoiMode = SpecificEoi;
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__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
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/* And now fail since this was spurious */
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return FALSE;
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}
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/* Do normal interrupt dismiss */
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return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
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}
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq13(IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql)
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{
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/* Clear the FPU busy latch */
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__outbyte(0xF0, 0);
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/* Do normal interrupt dismiss */
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return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
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}
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BOOLEAN
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__attribute__((regparm(3)))
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HalpDismissIrq07(IN KIRQL Irql,
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IN ULONG Irq,
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OUT PKIRQL OldIrql)
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{
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I8259_OCW3 Ocw3;
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I8259_ISR Isr;
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/* Request the ISR */
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Ocw3.Bits = 0;
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Ocw3.Sbo = 1;
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Ocw3.ReadRequest = ReadIsr;
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__outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
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/* Read the ISR */
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Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
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/* Is IRQ 7 really active? If it isn't, this is spurious so fail */
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if (Isr.Irq7 == FALSE) return FALSE;
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/* Do normal interrupt dismiss */
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return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
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}
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/* SYSTEM INTERRUPTS **********************************************************/
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/*
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@ -420,3 +605,19 @@ HalDisableSystemInterrupt(IN UCHAR Vector,
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/* Bring interrupts back */
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_enable();
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}
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/*
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* @implemented
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*/
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BOOLEAN
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NTAPI
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HalBeginSystemInterrupt(IN KIRQL Irql,
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IN UCHAR Vector,
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OUT PKIRQL OldIrql)
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{
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ULONG Irq;
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/* Get the IRQ and call the proper routine to handle it */
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Irq = Vector - PRIMARY_VECTOR_BASE;
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return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql);
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}
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@ -179,6 +179,26 @@ typedef enum _I8259_ICW4_BUFFERED_MODE
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BufferedMaster
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} I8259_ICW4_BUFFERED_MODE;
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typedef enum _I8259_READ_REQUEST
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{
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InvalidRequest,
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InvalidRequest2,
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ReadIdr,
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ReadIsr
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} I8259_READ_REQUEST;
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typedef enum _I8259_EOI_MODE
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{
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RotateAutoEoiClear,
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NonSpecificEoi,
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InvalidEoiMode,
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SpecificEoi,
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RotateAutoEoiSet,
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RotateNonSpecific,
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SetPriority,
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RotateSpecific
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} I8259_EOI_MODE;
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//
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// Definitions for ICW Registers
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//
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@ -243,6 +263,52 @@ typedef union _I8259_ICW4
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UCHAR Bits;
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} I8259_ICW4, *PI8259_ICW4;
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typedef union _I8259_OCW2
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{
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struct
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{
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UCHAR IrqNumber:3;
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UCHAR Sbz:2;
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I8259_EOI_MODE EoiMode:3;
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};
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UCHAR Bits;
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} I8259_OCW2, *PI8259_OCW2;
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typedef union _I8259_OCW3
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{
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struct
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{
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I8259_READ_REQUEST ReadRequest:2;
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UCHAR PollCommand:1;
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UCHAR Sbo:1;
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UCHAR Sbz:1;
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UCHAR SpecialMaskMode:2;
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UCHAR Reserved:1;
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};
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UCHAR Bits;
|
||||
} I8259_OCW3, *PI8259_OCW3;
|
||||
|
||||
typedef union _I8259_ISR
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Irq0:1;
|
||||
UCHAR Irq1:1;
|
||||
UCHAR Irq2:1;
|
||||
UCHAR Irq3:1;
|
||||
UCHAR Irq4:1;
|
||||
UCHAR Irq5:1;
|
||||
UCHAR Irq6:1;
|
||||
UCHAR Irq7:1;
|
||||
};
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ISR, *PI8259_ISR;
|
||||
|
||||
typedef I8259_ISR I8259_IDR, *PI8259_IDR;
|
||||
|
||||
//
|
||||
// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
|
||||
// P. 34, 35
|
||||
|
|
@ -295,6 +361,53 @@ typedef struct _PIC_MASK
|
|||
};
|
||||
} PIC_MASK, *PPIC_MASK;
|
||||
|
||||
typedef
|
||||
VOID
|
||||
(*PHAL_SW_INTERRUPT_HANDLER)(
|
||||
VOID
|
||||
);
|
||||
|
||||
typedef
|
||||
BOOLEAN
|
||||
__attribute__((regparm(3)))
|
||||
(*PHAL_DISMISS_INTERRUPT)(
|
||||
IN KIRQL Irql,
|
||||
IN ULONG Irq,
|
||||
OUT PKIRQL OldIrql
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
__attribute__((regparm(3)))
|
||||
HalpDismissIrqGeneric(
|
||||
IN KIRQL Irql,
|
||||
IN ULONG Irq,
|
||||
OUT PKIRQL OldIrql
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
__attribute__((regparm(3)))
|
||||
HalpDismissIrq15(
|
||||
IN KIRQL Irql,
|
||||
IN ULONG Irq,
|
||||
OUT PKIRQL OldIrql
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
__attribute__((regparm(3)))
|
||||
HalpDismissIrq13(
|
||||
IN KIRQL Irql,
|
||||
IN ULONG Irq,
|
||||
OUT PKIRQL OldIrql
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
__attribute__((regparm(3)))
|
||||
HalpDismissIrq07(
|
||||
IN KIRQL Irql,
|
||||
IN ULONG Irq,
|
||||
OUT PKIRQL OldIrql
|
||||
);
|
||||
|
||||
//
|
||||
// Mm PTE/PDE to Hal PTE/PDE
|
||||
//
|
||||
|
|
|
|||
Loading…
Reference in a new issue