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compatability fixes, so some hal code can be shared

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svn path=/branches/ros-amd64-bringup/; revision=35902
This commit is contained in:
Timo Kreuzer 2008-09-03 00:44:50 +00:00
parent 24326fcfd3
commit 89f1272447
4 changed files with 21 additions and 6 deletions
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4
reactos/hal/halx86/generic/timer.c
View file

@ -48,7 +48,7 @@ HalpInitializeClock(VOID)
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG Increment;
USHORT RollOver;
ULONG Flags = 0;
ULONG_PTR Flags = 0;
/* Check the CPU Type */
if (Prcb->CpuType <= 4)
@ -92,7 +92,7 @@ NTAPI
HalCalibratePerformanceCounter(IN volatile PLONG Count,
IN ULONGLONG NewCount)
{
ULONG Flags = 0;
ULONG_PTR Flags = 0;
/* Disable interrupts */
Ke386SaveFlags(Flags);

8
reactos/hal/halx86/include/bus.h
View file

@ -43,7 +43,7 @@
#define TYPE1_READ(x, y) \
TYPE1_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i)); \
READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
TYPE1_END(y)
//
@ -51,7 +51,7 @@
//
#define TYPE1_WRITE(x, y) \
TYPE1_START(x, y) \
WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i), \
WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
*((POINTER_TO_(y))Buffer)); \
TYPE1_END(y)
@ -69,7 +69,7 @@
#define TYPE2_READ(x, y) \
TYPE2_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT); \
READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
TYPE2_END(y)
//
@ -77,7 +77,7 @@
//
#define TYPE2_WRITE(x, y) \
TYPE2_START(x, y) \
WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT, \
WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
*((POINTER_TO_(y))Buffer)); \
TYPE2_END(y)

4
reactos/hal/halx86/include/hal.h
View file

@ -35,7 +35,11 @@
/* Internal kernel headers */
#include "internal/pci.h"
#ifdef _M_AMD64
#include "internal/amd64/intrin_i.h"
#else
#include "internal/i386/intrin_i.h"
#endif
/* Internal HAL Headers */
#include "apic.h"

11
reactos/hal/halx86/include/halp.h
View file

@ -154,6 +154,17 @@ HalpTrap06(
VOID
);
#ifdef _M_AMD64
#define KfLowerIrql KeLowerIrql
#ifndef CONFIG_SMP
/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
#define KiAcquireSpinLock(SpinLock)
#define KiReleaseSpinLock(SpinLock)
#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
#endif // !CONFIG_SMP
#endif // _M_AMD64
extern PVOID HalpRealModeStart;
extern PVOID HalpRealModeEnd;