mirror of
https://github.com/reactos/reactos.git
synced 2024-10-04 08:25:53 +00:00
Use generic HAL header
svn path=/trunk/; revision=16040
This commit is contained in:
parent
f8d053290e
commit
99cc88158b
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@ -6,13 +6,13 @@
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#define __INTERNAL_HAL_BUS_H
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typedef NTSTATUS STDCALL_FUNC
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(*pAdjustResourceList)(IN PBUS_HANDLER BusHandler,
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typedef NTSTATUS
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(STDCALL *pAdjustResourceList)(IN PBUS_HANDLER BusHandler,
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IN ULONG BusNumber,
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IN OUT PCM_RESOURCE_LIST Resources);
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typedef NTSTATUS STDCALL_FUNC
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(*pAssignSlotResources)(IN PBUS_HANDLER BusHandler,
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typedef NTSTATUS
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(STDCALL *pAssignSlotResources)(IN PBUS_HANDLER BusHandler,
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IN ULONG BusNumber,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName,
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@ -21,24 +21,24 @@ typedef NTSTATUS STDCALL_FUNC
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IN ULONG SlotNumber,
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IN OUT PCM_RESOURCE_LIST *AllocatedResources);
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typedef ULONG STDCALL_FUNC
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(*pGetSetBusData)(IN PBUS_HANDLER BusHandler,
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typedef ULONG
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(STDCALL *pGetSetBusData)(IN PBUS_HANDLER BusHandler,
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IN ULONG BusNumber,
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IN ULONG SlotNumber,
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OUT PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length);
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typedef ULONG STDCALL_FUNC
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(*pGetInterruptVector)(IN PBUS_HANDLER BusHandler,
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typedef ULONG
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(STDCALL *pGetInterruptVector)(IN PBUS_HANDLER BusHandler,
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IN ULONG BusNumber,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity);
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typedef ULONG STDCALL_FUNC
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(*pTranslateBusAddress)(IN PBUS_HANDLER BusHandler,
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typedef ULONG
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(STDCALL *pTranslateBusAddress)(IN PBUS_HANDLER BusHandler,
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IN ULONG BusNumber,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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@ -1,448 +1,74 @@
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/*
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*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS Hardware Abstraction Layer
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* FILE: hal/halx86/include/hal.h
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* PURPOSE: HAL Header
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* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
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*/
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#ifndef __INTERNAL_HAL_HAL_H
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#define __INTERNAL_HAL_HAL_H
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/* INCLUDES ******************************************************************/
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#define HAL_APC_REQUEST 0
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#define HAL_DPC_REQUEST 1
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/* SDK/DDK/NDK Headers. */
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#include <ddk/ntddk.h>
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#include <stdio.h>
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/* display.c */
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VOID FASTCALL HalInitializeDisplay (PLOADER_PARAMETER_BLOCK LoaderBlock);
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VOID FASTCALL HalClearDisplay (UCHAR CharAttribute);
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/* FIXME: NDK Headers */
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#include <ntos/types.h>
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#include <ntos/haltypes.h>
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#include <ntos/halfuncs.h>
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/* adapter.c */
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PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
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/* bus.c */
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VOID HalpInitBusHandlers (VOID);
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/* Internal Kernel Headers */
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//#include <internal/mm.h>
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#include <internal/ke.h>
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#include <internal/i386/ps.h>
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/* irql.c */
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VOID HalpInitPICs(VOID);
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//Temporary hack below.
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PVOID STDCALL
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MmAllocateContiguousAlignedMemory(IN ULONG NumberOfBytes,
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IN PHYSICAL_ADDRESS LowestAcceptableAddress,
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IN PHYSICAL_ADDRESS HighestAcceptableAddress,
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IN PHYSICAL_ADDRESS BoundaryAddressMultiple OPTIONAL,
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IN MEMORY_CACHING_TYPE CacheType OPTIONAL,
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IN ULONG Alignment);
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/* FIXME: NDK */
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VOID STDCALL KeEnterKernelDebugger (VOID);
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VOID FASTCALL KiAcquireSpinLock(PKSPIN_LOCK SpinLock);
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VOID FASTCALL KiReleaseSpinLock(PKSPIN_LOCK SpinLock);
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VOID STDCALL KiDispatchInterrupt(VOID);
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NTSTATUS
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STDCALL
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ObCreateObject (
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IN KPROCESSOR_MODE ObjectAttributesAccessMode OPTIONAL,
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IN POBJECT_TYPE ObjectType,
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IN POBJECT_ATTRIBUTES ObjectAttributes OPTIONAL,
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IN KPROCESSOR_MODE AccessMode,
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IN OUT PVOID ParseContext OPTIONAL,
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IN ULONG ObjectSize,
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IN ULONG PagedPoolCharge OPTIONAL,
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IN ULONG NonPagedPoolCharge OPTIONAL,
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OUT PVOID *Object
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);
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/* udelay.c */
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VOID HalpCalibrateStallExecution(VOID);
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/* Debug Header */
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#include <debug.h>
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/* pci.c */
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VOID HalpInitPciBus (VOID);
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/* Internal HAL Headers */
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#include "apic.h"
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#include "bus.h"
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#include "halirq.h"
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#include "halp.h"
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#include "mps.h"
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#include "ioapic.h"
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/* enum.c */
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VOID HalpStartEnumerator (VOID);
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/* dma.c */
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VOID HalpInitDma (VOID);
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/* mem.c */
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PVOID HalpMapPhysMemory(ULONG PhysAddr, ULONG Size);
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/* Non-generic initialization */
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VOID HalpInitPhase0 (VOID);
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/* DMA Page Register Structure
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080 DMA RESERVED
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081 DMA Page Register (channel 2)
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082 DMA Page Register (channel 3)
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083 DMA Page Register (channel 1)
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084 DMA RESERVED
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085 DMA RESERVED
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086 DMA RESERVED
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087 DMA Page Register (channel 0)
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088 DMA RESERVED
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089 PS/2-DMA Page Register (channel 6)
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08A PS/2-DMA Page Register (channel 7)
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08B PS/2-DMA Page Register (channel 5)
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08C PS/2-DMA RESERVED
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08D PS/2-DMA RESERVED
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08E PS/2-DMA RESERVED
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08F PS/2-DMA Page Register (channel 4)
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*/
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typedef struct _DMA_PAGE{
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UCHAR Reserved1;
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UCHAR Channel2;
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UCHAR Channel3;
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UCHAR Channel1;
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UCHAR Reserved2[3];
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UCHAR Channel0;
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UCHAR Reserved3;
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UCHAR Channel6;
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UCHAR Channel7;
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UCHAR Channel5;
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UCHAR Reserved4[3];
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UCHAR Channel4;
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} DMA_PAGE, *PDMA_PAGE;
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/* DMA Channel Mask Register Structure
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MSB LSB
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x x x x x x x x
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------------------- - -----
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| | | 00 - Select channel 0 mask bit
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| | \---- 01 - Select channel 1 mask bit
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| | 10 - Select channel 2 mask bit
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| | 11 - Select channel 3 mask bit
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| |
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| \---------- 0 - Clear mask bit
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| 1 - Set mask bit
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\----------------------- xx - Reserved
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*/
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typedef struct _DMA_CHANNEL_MASK {
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UCHAR Channel : 2;
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UCHAR SetMask : 1;
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UCHAR Reserved : 5;
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} DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
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/* DMA Mask Register Structure
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MSB LSB
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x x x x x x x x
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\---/ - - ----- -----
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| | | | | 00 - Channel 0 select
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| | | | \---- 01 - Channel 1 select
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| | | | 10 - Channel 2 select
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| | | | 11 - Channel 3 select
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| | | |
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| | | | 00 - Verify transfer
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| | | \------------ 01 - Write transfer
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| | | 10 - Read transfer
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| | |
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| | \-------------------- 0 - Autoinitialized
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| | 1 - Non-autoinitialized
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| |
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| \------------------------ 0 - Address increment select
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| 00 - Demand mode
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\------------------------------ 01 - Single mode
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10 - Block mode
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11 - Cascade mode
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*/
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typedef struct _DMA_MODE {
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UCHAR Channel : 2;
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UCHAR TransferType : 2;
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UCHAR AutoInitialize : 1;
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UCHAR AddressDecrement : 1;
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UCHAR RequestMode : 2;
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} DMA_MODE, *PDMA_MODE;
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/* DMA Extended Mode Register Structure
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MSB LSB
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x x x x x x x x
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- - ----- ----- -----
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| | | | | 00 - Channel 0 select
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| | | | \---- 01 - Channel 1 select
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| | | | 10 - Channel 2 select
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| | | | 11 - Channel 3 select
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| | | |
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| | | | 00 - 8-bit I/O, by bytes
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| | | \------------ 01 - 16-bit I/O, by words, address shifted
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| | | 10 - 32-bit I/O, by bytes
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| | | 11 - 16-bit I/O, by bytes
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| | |
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| | \---------------------- 00 - Compatible
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| | 01 - Type A
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| | 10 - Type B
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| | 11 - Burst
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| |
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| \---------------------------- 0 - Terminal Count is Output
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\---------------------------------0 - Disable Stop Register
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1 - Enable Stop Register
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*/
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typedef struct _DMA_EXTENDED_MODE {
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UCHAR ChannelNumber : 2;
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UCHAR TransferSize : 2;
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UCHAR TimingMode : 2;
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UCHAR TerminalCountIsOutput : 1;
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UCHAR EnableStopRegister : 1;
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}DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
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/* DMA Extended Mode Register Transfer Sizes */
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#define B_8BITS 0
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#define W_16BITS 1
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#define B_32BITS 2
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#define B_16BITS 3
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/* DMA Extended Mode Register Timing */
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#define COMPATIBLE_TIMING 0
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#define TYPE_A_TIMING 1
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#define TYPE_B_TIMING 2
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#define BURST_TIMING 3
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/* Channel Stop Registers for each Channel */
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typedef struct _DMA_CHANNEL_STOP {
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UCHAR ChannelLow;
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UCHAR ChannelMid;
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UCHAR ChannelHigh;
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UCHAR Reserved;
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} DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
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/* Transfer Types */
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#define VERIFY_TRANSFER 0x00
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#define READ_TRANSFER 0x01
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#define WRITE_TRANSFER 0x02
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/* Request Modes */
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#define DEMAND_REQUEST_MODE 0x00
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#define SINGLE_REQUEST_MODE 0x01
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#define BLOCK_REQUEST_MODE 0x02
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#define CASCADE_REQUEST_MODE 0x03
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#define DMA_SETMASK 4
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#define DMA_CLEARMASK 0
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#define DMA_READ 4
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#define DMA_WRITE 8
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#define DMA_SINGLE_TRANSFER 0x40
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#define DMA_AUTO_INIT 0x10
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typedef struct _DMA1_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR DmaBaseCount;
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} DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
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typedef struct _DMA2_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR Reserved1;
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UCHAR DmaBaseCount;
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UCHAR Reserved2;
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} DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
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typedef struct _DMA1_CONTROL {
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DMA1_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR DmaRequest;
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UCHAR SingleMask;
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UCHAR Mode;
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UCHAR ClearBytePointer;
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UCHAR MasterClear;
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UCHAR ClearMask;
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UCHAR AllMask;
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} DMA1_CONTROL, *PDMA1_CONTROL;
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typedef struct _DMA2_CONTROL {
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DMA2_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR Reserved1;
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UCHAR DmaRequest;
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UCHAR Reserved2;
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UCHAR SingleMask;
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UCHAR Reserved3;
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UCHAR Mode;
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UCHAR Reserved4;
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UCHAR ClearBytePointer;
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UCHAR Reserved5;
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UCHAR MasterClear;
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UCHAR Reserved6;
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UCHAR ClearMask;
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UCHAR Reserved7;
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UCHAR AllMask;
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UCHAR Reserved8;
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} DMA2_CONTROL, *PDMA2_CONTROL;
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/* This Structure Defines the I/O Map of the 82537 Controller
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I've only defined the registers which are likely to be useful to us */
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typedef struct _EISA_CONTROL {
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/* DMA Controller 1 */
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DMA1_CONTROL DmaController1; /* 00h-0Fh */
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UCHAR Reserved1[16]; /* 0Fh-1Fh */
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/* Interrupt Controller 1 (PIC) */
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UCHAR Pic1Operation; /* 20h */
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UCHAR Pic1Interrupt; /* 21h */
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UCHAR Reserved2[30]; /* 22h-3Fh */
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/* Timer */
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UCHAR TimerCounter; /* 40h */
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UCHAR TimerMemoryRefresh; /* 41h */
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UCHAR Speaker; /* 42h */
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UCHAR TimerOperation; /* 43h */
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UCHAR TimerMisc; /* 44h */
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UCHAR Reserved3[2]; /* 45-46h */
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UCHAR TimerCounterControl; /* 47h */
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UCHAR TimerFailSafeCounter; /* 48h */
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UCHAR Reserved4; /* 49h */
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UCHAR TimerCounter2; /* 4Ah */
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UCHAR TimerOperation2; /* 4Bh */
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UCHAR Reserved5[20]; /* 4Ch-5Fh */
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/* NMI / Keyboard / RTC */
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UCHAR Keyboard; /* 60h */
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UCHAR NmiStatus; /* 61h */
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UCHAR Reserved6[14]; /* 62h-6Fh */
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UCHAR NmiEnable; /* 70h */
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UCHAR Reserved7[15]; /* 71h-7Fh */
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/* DMA Page Registers Controller 1 */
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DMA_PAGE DmaController1Pages; /* 80h-8Fh */
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UCHAR Reserved8[16]; /* 90h-9Fh */
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/* Interrupt Controller 2 (PIC) */
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UCHAR Pic2Operation; /* 0A0h */
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UCHAR Pic2Interrupt; /* 0A1h */
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UCHAR Reserved9[30]; /* 0A2h-0BFh */
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/* DMA Controller 2 */
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DMA1_CONTROL DmaController2; /* 0C0h-0CFh */
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/* System Reserved Ports */
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UCHAR SystemReserved[816]; /* 0D0h-3FFh */
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/* Extended DMA Registers, Controller 1 */
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UCHAR DmaHighByteCount1[8]; /* 400h-407h */
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UCHAR Reserved10[2]; /* 408h-409h */
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UCHAR DmaChainMode1; /* 40Ah */
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UCHAR DmaExtendedMode1; /* 40Bh */
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UCHAR DmaBufferControl; /* 40Ch */
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UCHAR Reserved11[84]; /* 40Dh-460h */
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UCHAR ExtendedNmiControl; /* 461h */
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UCHAR NmiCommand; /* 462h */
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UCHAR Reserved12; /* 463h */
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UCHAR BusMaster; /* 464h */
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UCHAR Reserved13[27]; /* 465h-47Fh */
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/* DMA Page Registers Controller 2 */
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DMA_PAGE DmaController2Pages; /* 480h-48Fh */
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UCHAR Reserved14[48]; /* 490h-4BFh */
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/* Extended DMA Registers, Controller 2 */
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UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */
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/* Edge/Level Control Registers */
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UCHAR Pic1EdgeLevel; /* 4D0h */
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UCHAR Pic2EdgeLevel; /* 4D1h */
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UCHAR Reserved15[2]; /* 4D2h-4D3h */
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/* Extended DMA Registers, Controller 2 */
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UCHAR DmaChainMode2; /* 4D4h */
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UCHAR Reserved16; /* 4D5h */
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UCHAR DmaExtendedMode2; /* 4D6h */
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UCHAR Reserved17[9]; /* 4D7h-4DFh */
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/* DMA Stop Registers */
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DMA_CHANNEL_STOP DmaChannelStop[8]; /* 4E0h-4FFh */
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} EISA_CONTROL, *PEISA_CONTROL;
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extern ULONG HalpEisaDma;
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extern PADAPTER_OBJECT MasterAdapter;
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EXPORTED ULONG HalpEisaDma;
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EXPORTED PADAPTER_OBJECT MasterAdapter;
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/*
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* ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
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*
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* NOTES:
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* - I've updated this to the Windows Object Defintion.
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*/
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struct _ADAPTER_OBJECT {
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DMA_ADAPTER DmaHeader;
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struct _ADAPTER_OBJECT *MasterAdapter;
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ULONG MapRegistersPerChannel;
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PVOID AdapterBaseVa;
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PVOID MapRegisterBase;
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ULONG NumberOfMapRegisters;
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ULONG CommittedMapRegisters;
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PWAIT_CONTEXT_BLOCK CurrentWcb;
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KDEVICE_QUEUE ChannelWaitQueue;
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PKDEVICE_QUEUE RegisterWaitQueue;
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LIST_ENTRY AdapterQueue;
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ULONG SpinLock;
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PRTL_BITMAP MapRegisters;
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PUCHAR PagePort;
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UCHAR ChannelNumber;
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UCHAR AdapterNumber;
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USHORT DmaPortAddress;
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union {
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DMA_MODE AdapterMode;
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UCHAR AdapterModeByte;
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};
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BOOLEAN NeedsMapRegisters;
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BOOLEAN MasterDevice;
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UCHAR Width16Bits;
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UCHAR ScatterGather;
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UCHAR IgnoreCount;
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UCHAR Dma32BitAddresses;
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UCHAR Dma64BitAddresses;
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BOOLEAN LegacyAdapter;
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LIST_ENTRY AdapterList;
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};
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/*
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struct _ADAPTER_OBJECT {
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INTERFACE_TYPE InterfaceType;
|
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BOOLEAN Master;
|
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int Channel;
|
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PVOID PagePort;
|
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PVOID CountPort;
|
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PVOID OffsetPort;
|
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KSPIN_LOCK SpinLock;
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PVOID Buffer;
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BOOLEAN Inuse;
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ULONG AvailableMapRegisters;
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PVOID MapRegisterBase;
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ULONG AllocatedMapRegisters;
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||||
PWAIT_CONTEXT_BLOCK WaitContextBlock;
|
||||
KDEVICE_QUEUE DeviceQueue;
|
||||
BOOLEAN ScatterGather;
|
||||
BOOLEAN DemandMode;
|
||||
BOOLEAN AutoInitialize;
|
||||
};
|
||||
*/
|
||||
|
||||
/* sysinfo.c */
|
||||
NTSTATUS STDCALL
|
||||
HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
|
||||
IN ULONG BufferSize,
|
||||
IN OUT PVOID Buffer,
|
||||
OUT PULONG ReturnedLength);
|
||||
|
||||
|
||||
/* Non-standard functions */
|
||||
VOID STDCALL
|
||||
HalReleaseDisplayOwnership();
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalQueryDisplayOwnership();
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#define Ki386SaveFlags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
|
||||
#define Ki386RestoreFlags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
|
||||
#define Ki386DisableInterrupts() __asm__ __volatile__("cli\n\t")
|
||||
#define Ki386EnableInterrupts() __asm__ __volatile__("sti\n\t")
|
||||
#define Ki386HaltProcessor() __asm__ __volatile__("hlt\n\t")
|
||||
#define Ki386RdTSC(x) __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
|
||||
#define Ki386Rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
|
||||
#define Ki386Wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : /* no outputs */ : "c" (msr), "a" (val1), "d" (val2))
|
||||
|
||||
static inline BYTE Ki386ReadFsByte(ULONG offset)
|
||||
{
|
||||
BYTE b;
|
||||
__asm__ __volatile__("movb %%fs:(%1),%0":"=q" (b):"r" (offset));
|
||||
return b;
|
||||
}
|
||||
|
||||
static inline VOID Ki386WriteFsByte(ULONG offset, BYTE value)
|
||||
{
|
||||
__asm__ __volatile__("movb %0,%%fs:(%1)"::"r" (value), "r" (offset));
|
||||
}
|
||||
|
||||
#elif defined(_MSC_VER)
|
||||
#define Ki386SaveFlags(x) __asm pushfd __asm pop x;
|
||||
#define Ki386RestoreFlags(x) __asm push x __asm popfd;
|
||||
#define Ki386DisableInterrupts() __asm cli
|
||||
#define Ki386EnableInterrupts() __asm sti
|
||||
#define Ki386HaltProcessor() __asm hlt
|
||||
#else
|
||||
#error Unknown compiler for inline assembler
|
||||
/* Helper Macros FIXME: NDK */
|
||||
#define ROUNDUP(a,b) ((((a)+(b)-1)/(b))*(b))
|
||||
#define ROUND_DOWN(N, S) ((N) - ((N) % (S)))
|
||||
#ifndef HIWORD
|
||||
#define HIWORD(l) ((WORD)(((DWORD)(l) >> 16) & 0xFFFF))
|
||||
#endif
|
||||
#ifndef LOWORD
|
||||
#define LOWORD(l) ((WORD)(l))
|
||||
#endif
|
||||
|
||||
typedef struct tagHALP_HOOKS
|
||||
{
|
||||
void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
|
||||
} HALP_HOOKS, *PHALP_HOOKS;
|
||||
|
||||
extern HALP_HOOKS HalpHooks;
|
||||
|
||||
#endif /* __INTERNAL_HAL_HAL_H */
|
||||
/* EOF */
|
||||
|
|
449
reactos/hal/halx86/include/halp.h
Normal file
449
reactos/hal/halx86/include/halp.h
Normal file
|
@ -0,0 +1,449 @@
|
|||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __INTERNAL_HAL_HAL_H
|
||||
#define __INTERNAL_HAL_HAL_H
|
||||
|
||||
#define HAL_APC_REQUEST 0
|
||||
#define HAL_DPC_REQUEST 1
|
||||
|
||||
/* display.c */
|
||||
struct _LOADER_PARAMETER_BLOCK;
|
||||
VOID FASTCALL HalInitializeDisplay (struct _LOADER_PARAMETER_BLOCK *LoaderBlock);
|
||||
VOID FASTCALL HalClearDisplay (UCHAR CharAttribute);
|
||||
|
||||
/* adapter.c */
|
||||
PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
|
||||
|
||||
/* bus.c */
|
||||
VOID HalpInitBusHandlers (VOID);
|
||||
|
||||
/* irql.c */
|
||||
VOID HalpInitPICs(VOID);
|
||||
|
||||
/* udelay.c */
|
||||
VOID HalpCalibrateStallExecution(VOID);
|
||||
|
||||
/* pci.c */
|
||||
VOID HalpInitPciBus (VOID);
|
||||
|
||||
/* enum.c */
|
||||
VOID HalpStartEnumerator (VOID);
|
||||
|
||||
/* dma.c */
|
||||
VOID HalpInitDma (VOID);
|
||||
|
||||
/* mem.c */
|
||||
PVOID HalpMapPhysMemory(ULONG PhysAddr, ULONG Size);
|
||||
|
||||
/* Non-generic initialization */
|
||||
VOID HalpInitPhase0 (VOID);
|
||||
|
||||
/* DMA Page Register Structure
|
||||
080 DMA RESERVED
|
||||
081 DMA Page Register (channel 2)
|
||||
082 DMA Page Register (channel 3)
|
||||
083 DMA Page Register (channel 1)
|
||||
084 DMA RESERVED
|
||||
085 DMA RESERVED
|
||||
086 DMA RESERVED
|
||||
087 DMA Page Register (channel 0)
|
||||
088 DMA RESERVED
|
||||
089 PS/2-DMA Page Register (channel 6)
|
||||
08A PS/2-DMA Page Register (channel 7)
|
||||
08B PS/2-DMA Page Register (channel 5)
|
||||
08C PS/2-DMA RESERVED
|
||||
08D PS/2-DMA RESERVED
|
||||
08E PS/2-DMA RESERVED
|
||||
08F PS/2-DMA Page Register (channel 4)
|
||||
*/
|
||||
typedef struct _DMA_PAGE{
|
||||
UCHAR Reserved1;
|
||||
UCHAR Channel2;
|
||||
UCHAR Channel3;
|
||||
UCHAR Channel1;
|
||||
UCHAR Reserved2[3];
|
||||
UCHAR Channel0;
|
||||
UCHAR Reserved3;
|
||||
UCHAR Channel6;
|
||||
UCHAR Channel7;
|
||||
UCHAR Channel5;
|
||||
UCHAR Reserved4[3];
|
||||
UCHAR Channel4;
|
||||
} DMA_PAGE, *PDMA_PAGE;
|
||||
|
||||
/* DMA Channel Mask Register Structure
|
||||
|
||||
MSB LSB
|
||||
x x x x x x x x
|
||||
------------------- - -----
|
||||
| | | 00 - Select channel 0 mask bit
|
||||
| | \---- 01 - Select channel 1 mask bit
|
||||
| | 10 - Select channel 2 mask bit
|
||||
| | 11 - Select channel 3 mask bit
|
||||
| |
|
||||
| \---------- 0 - Clear mask bit
|
||||
| 1 - Set mask bit
|
||||
|
|
||||
\----------------------- xx - Reserved
|
||||
*/
|
||||
typedef struct _DMA_CHANNEL_MASK {
|
||||
UCHAR Channel : 2;
|
||||
UCHAR SetMask : 1;
|
||||
UCHAR Reserved : 5;
|
||||
} DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
|
||||
|
||||
/* DMA Mask Register Structure
|
||||
|
||||
MSB LSB
|
||||
x x x x x x x x
|
||||
\---/ - - ----- -----
|
||||
| | | | | 00 - Channel 0 select
|
||||
| | | | \---- 01 - Channel 1 select
|
||||
| | | | 10 - Channel 2 select
|
||||
| | | | 11 - Channel 3 select
|
||||
| | | |
|
||||
| | | | 00 - Verify transfer
|
||||
| | | \------------ 01 - Write transfer
|
||||
| | | 10 - Read transfer
|
||||
| | |
|
||||
| | \-------------------- 0 - Autoinitialized
|
||||
| | 1 - Non-autoinitialized
|
||||
| |
|
||||
| \------------------------ 0 - Address increment select
|
||||
|
|
||||
| 00 - Demand mode
|
||||
\------------------------------ 01 - Single mode
|
||||
10 - Block mode
|
||||
11 - Cascade mode
|
||||
*/
|
||||
typedef struct _DMA_MODE {
|
||||
UCHAR Channel : 2;
|
||||
UCHAR TransferType : 2;
|
||||
UCHAR AutoInitialize : 1;
|
||||
UCHAR AddressDecrement : 1;
|
||||
UCHAR RequestMode : 2;
|
||||
} DMA_MODE, *PDMA_MODE;
|
||||
|
||||
|
||||
/* DMA Extended Mode Register Structure
|
||||
|
||||
MSB LSB
|
||||
x x x x x x x x
|
||||
- - ----- ----- -----
|
||||
| | | | | 00 - Channel 0 select
|
||||
| | | | \---- 01 - Channel 1 select
|
||||
| | | | 10 - Channel 2 select
|
||||
| | | | 11 - Channel 3 select
|
||||
| | | |
|
||||
| | | | 00 - 8-bit I/O, by bytes
|
||||
| | | \------------ 01 - 16-bit I/O, by words, address shifted
|
||||
| | | 10 - 32-bit I/O, by bytes
|
||||
| | | 11 - 16-bit I/O, by bytes
|
||||
| | |
|
||||
| | \---------------------- 00 - Compatible
|
||||
| | 01 - Type A
|
||||
| | 10 - Type B
|
||||
| | 11 - Burst
|
||||
| |
|
||||
| \---------------------------- 0 - Terminal Count is Output
|
||||
|
|
||||
\---------------------------------0 - Disable Stop Register
|
||||
1 - Enable Stop Register
|
||||
*/
|
||||
typedef struct _DMA_EXTENDED_MODE {
|
||||
UCHAR ChannelNumber : 2;
|
||||
UCHAR TransferSize : 2;
|
||||
UCHAR TimingMode : 2;
|
||||
UCHAR TerminalCountIsOutput : 1;
|
||||
UCHAR EnableStopRegister : 1;
|
||||
}DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
|
||||
|
||||
/* DMA Extended Mode Register Transfer Sizes */
|
||||
#define B_8BITS 0
|
||||
#define W_16BITS 1
|
||||
#define B_32BITS 2
|
||||
#define B_16BITS 3
|
||||
|
||||
/* DMA Extended Mode Register Timing */
|
||||
#define COMPATIBLE_TIMING 0
|
||||
#define TYPE_A_TIMING 1
|
||||
#define TYPE_B_TIMING 2
|
||||
#define BURST_TIMING 3
|
||||
|
||||
/* Channel Stop Registers for each Channel */
|
||||
typedef struct _DMA_CHANNEL_STOP {
|
||||
UCHAR ChannelLow;
|
||||
UCHAR ChannelMid;
|
||||
UCHAR ChannelHigh;
|
||||
UCHAR Reserved;
|
||||
} DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
|
||||
|
||||
/* Transfer Types */
|
||||
#define VERIFY_TRANSFER 0x00
|
||||
#define READ_TRANSFER 0x01
|
||||
#define WRITE_TRANSFER 0x02
|
||||
|
||||
/* Request Modes */
|
||||
#define DEMAND_REQUEST_MODE 0x00
|
||||
#define SINGLE_REQUEST_MODE 0x01
|
||||
#define BLOCK_REQUEST_MODE 0x02
|
||||
#define CASCADE_REQUEST_MODE 0x03
|
||||
|
||||
#define DMA_SETMASK 4
|
||||
#define DMA_CLEARMASK 0
|
||||
#define DMA_READ 4
|
||||
#define DMA_WRITE 8
|
||||
#define DMA_SINGLE_TRANSFER 0x40
|
||||
#define DMA_AUTO_INIT 0x10
|
||||
|
||||
typedef struct _DMA1_ADDRESS_COUNT {
|
||||
UCHAR DmaBaseAddress;
|
||||
UCHAR DmaBaseCount;
|
||||
} DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
|
||||
|
||||
typedef struct _DMA2_ADDRESS_COUNT {
|
||||
UCHAR DmaBaseAddress;
|
||||
UCHAR Reserved1;
|
||||
UCHAR DmaBaseCount;
|
||||
UCHAR Reserved2;
|
||||
} DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
|
||||
|
||||
typedef struct _DMA1_CONTROL {
|
||||
DMA1_ADDRESS_COUNT DmaAddressCount[4];
|
||||
UCHAR DmaStatus;
|
||||
UCHAR DmaRequest;
|
||||
UCHAR SingleMask;
|
||||
UCHAR Mode;
|
||||
UCHAR ClearBytePointer;
|
||||
UCHAR MasterClear;
|
||||
UCHAR ClearMask;
|
||||
UCHAR AllMask;
|
||||
} DMA1_CONTROL, *PDMA1_CONTROL;
|
||||
|
||||
typedef struct _DMA2_CONTROL {
|
||||
DMA2_ADDRESS_COUNT DmaAddressCount[4];
|
||||
UCHAR DmaStatus;
|
||||
UCHAR Reserved1;
|
||||
UCHAR DmaRequest;
|
||||
UCHAR Reserved2;
|
||||
UCHAR SingleMask;
|
||||
UCHAR Reserved3;
|
||||
UCHAR Mode;
|
||||
UCHAR Reserved4;
|
||||
UCHAR ClearBytePointer;
|
||||
UCHAR Reserved5;
|
||||
UCHAR MasterClear;
|
||||
UCHAR Reserved6;
|
||||
UCHAR ClearMask;
|
||||
UCHAR Reserved7;
|
||||
UCHAR AllMask;
|
||||
UCHAR Reserved8;
|
||||
} DMA2_CONTROL, *PDMA2_CONTROL;
|
||||
|
||||
/* This Structure Defines the I/O Map of the 82537 Controller
|
||||
I've only defined the registers which are likely to be useful to us */
|
||||
typedef struct _EISA_CONTROL {
|
||||
/* DMA Controller 1 */
|
||||
DMA1_CONTROL DmaController1; /* 00h-0Fh */
|
||||
UCHAR Reserved1[16]; /* 0Fh-1Fh */
|
||||
|
||||
/* Interrupt Controller 1 (PIC) */
|
||||
UCHAR Pic1Operation; /* 20h */
|
||||
UCHAR Pic1Interrupt; /* 21h */
|
||||
UCHAR Reserved2[30]; /* 22h-3Fh */
|
||||
|
||||
/* Timer */
|
||||
UCHAR TimerCounter; /* 40h */
|
||||
UCHAR TimerMemoryRefresh; /* 41h */
|
||||
UCHAR Speaker; /* 42h */
|
||||
UCHAR TimerOperation; /* 43h */
|
||||
UCHAR TimerMisc; /* 44h */
|
||||
UCHAR Reserved3[2]; /* 45-46h */
|
||||
UCHAR TimerCounterControl; /* 47h */
|
||||
UCHAR TimerFailSafeCounter; /* 48h */
|
||||
UCHAR Reserved4; /* 49h */
|
||||
UCHAR TimerCounter2; /* 4Ah */
|
||||
UCHAR TimerOperation2; /* 4Bh */
|
||||
UCHAR Reserved5[20]; /* 4Ch-5Fh */
|
||||
|
||||
/* NMI / Keyboard / RTC */
|
||||
UCHAR Keyboard; /* 60h */
|
||||
UCHAR NmiStatus; /* 61h */
|
||||
UCHAR Reserved6[14]; /* 62h-6Fh */
|
||||
UCHAR NmiEnable; /* 70h */
|
||||
UCHAR Reserved7[15]; /* 71h-7Fh */
|
||||
|
||||
/* DMA Page Registers Controller 1 */
|
||||
DMA_PAGE DmaController1Pages; /* 80h-8Fh */
|
||||
UCHAR Reserved8[16]; /* 90h-9Fh */
|
||||
|
||||
/* Interrupt Controller 2 (PIC) */
|
||||
UCHAR Pic2Operation; /* 0A0h */
|
||||
UCHAR Pic2Interrupt; /* 0A1h */
|
||||
UCHAR Reserved9[30]; /* 0A2h-0BFh */
|
||||
|
||||
/* DMA Controller 2 */
|
||||
DMA1_CONTROL DmaController2; /* 0C0h-0CFh */
|
||||
|
||||
/* System Reserved Ports */
|
||||
UCHAR SystemReserved[816]; /* 0D0h-3FFh */
|
||||
|
||||
/* Extended DMA Registers, Controller 1 */
|
||||
UCHAR DmaHighByteCount1[8]; /* 400h-407h */
|
||||
UCHAR Reserved10[2]; /* 408h-409h */
|
||||
UCHAR DmaChainMode1; /* 40Ah */
|
||||
UCHAR DmaExtendedMode1; /* 40Bh */
|
||||
UCHAR DmaBufferControl; /* 40Ch */
|
||||
UCHAR Reserved11[84]; /* 40Dh-460h */
|
||||
UCHAR ExtendedNmiControl; /* 461h */
|
||||
UCHAR NmiCommand; /* 462h */
|
||||
UCHAR Reserved12; /* 463h */
|
||||
UCHAR BusMaster; /* 464h */
|
||||
UCHAR Reserved13[27]; /* 465h-47Fh */
|
||||
|
||||
/* DMA Page Registers Controller 2 */
|
||||
DMA_PAGE DmaController2Pages; /* 480h-48Fh */
|
||||
UCHAR Reserved14[48]; /* 490h-4BFh */
|
||||
|
||||
/* Extended DMA Registers, Controller 2 */
|
||||
UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */
|
||||
|
||||
/* Edge/Level Control Registers */
|
||||
UCHAR Pic1EdgeLevel; /* 4D0h */
|
||||
UCHAR Pic2EdgeLevel; /* 4D1h */
|
||||
UCHAR Reserved15[2]; /* 4D2h-4D3h */
|
||||
|
||||
/* Extended DMA Registers, Controller 2 */
|
||||
UCHAR DmaChainMode2; /* 4D4h */
|
||||
UCHAR Reserved16; /* 4D5h */
|
||||
UCHAR DmaExtendedMode2; /* 4D6h */
|
||||
UCHAR Reserved17[9]; /* 4D7h-4DFh */
|
||||
|
||||
/* DMA Stop Registers */
|
||||
DMA_CHANNEL_STOP DmaChannelStop[8]; /* 4E0h-4FFh */
|
||||
} EISA_CONTROL, *PEISA_CONTROL;
|
||||
|
||||
extern ULONG HalpEisaDma;
|
||||
extern PADAPTER_OBJECT MasterAdapter;
|
||||
|
||||
ULONG HalpEisaDma;
|
||||
PADAPTER_OBJECT MasterAdapter;
|
||||
|
||||
/*
|
||||
* ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
|
||||
*
|
||||
* NOTES:
|
||||
* - I've updated this to the Windows Object Defintion.
|
||||
*/
|
||||
struct _ADAPTER_OBJECT {
|
||||
DMA_ADAPTER DmaHeader;
|
||||
struct _ADAPTER_OBJECT *MasterAdapter;
|
||||
ULONG MapRegistersPerChannel;
|
||||
PVOID AdapterBaseVa;
|
||||
PVOID MapRegisterBase;
|
||||
ULONG NumberOfMapRegisters;
|
||||
ULONG CommittedMapRegisters;
|
||||
PWAIT_CONTEXT_BLOCK CurrentWcb;
|
||||
KDEVICE_QUEUE ChannelWaitQueue;
|
||||
PKDEVICE_QUEUE RegisterWaitQueue;
|
||||
LIST_ENTRY AdapterQueue;
|
||||
ULONG SpinLock;
|
||||
PRTL_BITMAP MapRegisters;
|
||||
PUCHAR PagePort;
|
||||
UCHAR ChannelNumber;
|
||||
UCHAR AdapterNumber;
|
||||
USHORT DmaPortAddress;
|
||||
union {
|
||||
DMA_MODE AdapterMode;
|
||||
UCHAR AdapterModeByte;
|
||||
};
|
||||
BOOLEAN NeedsMapRegisters;
|
||||
BOOLEAN MasterDevice;
|
||||
UCHAR Width16Bits;
|
||||
UCHAR ScatterGather;
|
||||
UCHAR IgnoreCount;
|
||||
UCHAR Dma32BitAddresses;
|
||||
UCHAR Dma64BitAddresses;
|
||||
BOOLEAN LegacyAdapter;
|
||||
LIST_ENTRY AdapterList;
|
||||
} ADAPTER_OBJECT;
|
||||
|
||||
/*
|
||||
struct _ADAPTER_OBJECT {
|
||||
INTERFACE_TYPE InterfaceType;
|
||||
BOOLEAN Master;
|
||||
int Channel;
|
||||
PVOID PagePort;
|
||||
PVOID CountPort;
|
||||
PVOID OffsetPort;
|
||||
KSPIN_LOCK SpinLock;
|
||||
PVOID Buffer;
|
||||
BOOLEAN Inuse;
|
||||
ULONG AvailableMapRegisters;
|
||||
PVOID MapRegisterBase;
|
||||
ULONG AllocatedMapRegisters;
|
||||
PWAIT_CONTEXT_BLOCK WaitContextBlock;
|
||||
KDEVICE_QUEUE DeviceQueue;
|
||||
BOOLEAN ScatterGather;
|
||||
BOOLEAN DemandMode;
|
||||
BOOLEAN AutoInitialize;
|
||||
};
|
||||
*/
|
||||
|
||||
/* sysinfo.c */
|
||||
NTSTATUS STDCALL
|
||||
HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
|
||||
IN ULONG BufferSize,
|
||||
IN OUT PVOID Buffer,
|
||||
OUT PULONG ReturnedLength);
|
||||
|
||||
|
||||
/* Non-standard functions */
|
||||
VOID STDCALL
|
||||
HalReleaseDisplayOwnership();
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalQueryDisplayOwnership();
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#define Ki386SaveFlags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
|
||||
#define Ki386RestoreFlags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
|
||||
#define Ki386DisableInterrupts() __asm__ __volatile__("cli\n\t")
|
||||
#define Ki386EnableInterrupts() __asm__ __volatile__("sti\n\t")
|
||||
#define Ki386HaltProcessor() __asm__ __volatile__("hlt\n\t")
|
||||
#define Ki386RdTSC(x) __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
|
||||
#define Ki386Rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
|
||||
#define Ki386Wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : /* no outputs */ : "c" (msr), "a" (val1), "d" (val2))
|
||||
|
||||
static inline BYTE Ki386ReadFsByte(ULONG offset)
|
||||
{
|
||||
BYTE b;
|
||||
__asm__ __volatile__("movb %%fs:(%1),%0":"=q" (b):"r" (offset));
|
||||
return b;
|
||||
}
|
||||
|
||||
static inline VOID Ki386WriteFsByte(ULONG offset, BYTE value)
|
||||
{
|
||||
__asm__ __volatile__("movb %0,%%fs:(%1)"::"r" (value), "r" (offset));
|
||||
}
|
||||
|
||||
#elif defined(_MSC_VER)
|
||||
#define Ki386SaveFlags(x) __asm pushfd __asm pop x;
|
||||
#define Ki386RestoreFlags(x) __asm push x __asm popfd;
|
||||
#define Ki386DisableInterrupts() __asm cli
|
||||
#define Ki386EnableInterrupts() __asm sti
|
||||
#define Ki386HaltProcessor() __asm hlt
|
||||
#else
|
||||
#error Unknown compiler for inline assembler
|
||||
#endif
|
||||
|
||||
typedef struct tagHALP_HOOKS
|
||||
{
|
||||
void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
|
||||
} HALP_HOOKS, *PHALP_HOOKS;
|
||||
|
||||
extern HALP_HOOKS HalpHooks;
|
||||
|
||||
#endif /* __INTERNAL_HAL_HAL_H */
|
Loading…
Reference in a new issue