- Fix KiGeneralProtectionFault
- Don't bugcheck in KiUnexpectedInterrupt
- Remove debugprint in KiEndInterrupt, and instead assert, its called from the clock interrupt, since thats the only instance we handle right now
svn path=/trunk/; revision=53720
- add common amd64 asm trap macros
- fix amd64 version of HackEoi
- send EOI in amd64 trap exit code, so we avoid using HackEoi
- modify HalpClockInterruptHandler for better portability
- fix amd64 TscCalibrationISR
svn path=/trunk/; revision=53719
- get version.h and buildno.h out of precompiled headers, to avoid rebuilding the whole module each time we reconfigure the build
svn path=/trunk/; revision=53716
- Fix some stuff that gcc complains about. It doesn't like to use static data in non-static inline functions for some unknown reason.
- Implement support for level triggered interrupts, when using lazy irql
svn path=/trunk/; revision=53711
- Improve List_PaToVa, making the code cleaner
- Dereference LoaderBlock->Extension only after WinLdrSetProcessorContext, since its in kernel address space
svn path=/trunk/; revision=53710
- Move some shared constants (HYPERSPACE_BASE, MM_HAL_VA_START, APIC_BASE) to NDK to avoid duplicating them, also fix wrong values for amd64
- Map the hal address space in amd64 freeldr
- Fix use of uninitialized variable (HighPart of PHYSICAL_ADDRESS) in HalpAcpiCopyBiosTable
- Fix some MSVC and amd64 warnings
svn path=/trunk/; revision=53709
* Merge r53700. Point 3 in bug 6481 was fixed by fixing the parser (at line 414) to use only ',' as the delimiter, to match Windows behavior.
svn path=/trunk/; revision=53702
Implement lazy irql for APIC. This is useful for VMs, since APIC usually has high overhead due to the need of invoking the hypervisor on every irql raise and lower. With lazy irql we avoid that until absolutely neccessary. Note that we misuse the PCR's IRR field to save the current hardware irql. Its a huge performance boost (some parts take half the time), making APIC performance close to PIC performance on VBox. This is something that Windows doesn't have :)
svn path=/trunk/; revision=53695
- Create a volatile device tree during 1st stage so the new HAL that's loaded in 2nd stage can do proper enumeration without phantom devices from the old HAL
svn path=/trunk/; revision=53694
- Fix incorrect loop boundaries in the ARM version of MmCreateProcessAddressSpace. Spotted by Vincenzo Cotugno and cppcheck
- Correct outdated wineimport.cmd URL in README.WINE
- Assorted spelling and readability fixes
svn path=/trunk/; revision=53688
- Add support for guarded allocations, that can be used to detect buffer overruns
- Add GuardedMemory example test
- Add MmSection test with some basic parameter checks for MmCreateSection
- Fix some x64 build problems
- Update readme
svn path=/trunk/; revision=53687
- Add optional asynchronous io code for service control pipes. This is disabled by default due to bugs in NPFS.
- Read service pipe timeout value from the registry.
svn path=/trunk/; revision=53686
- End the interrupt in HalpApcInterruptHandler and HalpDispatchInterruptHandler before calling the kernel, otherwise we would be stuck at high processor irql
- Improve HalEnableSystemInterrupt
- disable interrupts in HalpInitializeClock
=> APIC hal boots to desktop!
svn path=/trunk/; revision=53685
The handlers for unexpected interrupts that we generate from asm macros use a push instruction with an 8 bit operand to push the interrupt number on the stack. Now the 8 bit push has the unfortunate behaviour of sign extending to 32 bit. But since the assembler is smart (or at least thinks so) it will not generate such a push instruction for values larger than 0x7f. This resulted in 7 bytes long stubs in the range of 0x30 .. 0x7f and 10 bytes long stubs after that. To fix this 128 is substracted from the value and later readded in the common code path. A second issue arose, because the assembler would start to use 8 bit relative short jumps as soon as the target was less than 127 bytes away, which happened for some of the higher interrupts, which then had a smaller stub then the others. Fix this by moving the stubs up in the code further away from the target label, so that always 32bit relative jumps will be used. These problems didn't show up so far, since we used the PIC and interrupts in the range of 0x30 .. 0x40 and the code that relied on the stubs all having the same length was working well. This changes with an APIC based hal, where interrupts of much higher number are likely to be used.
svn path=/trunk/; revision=53679
- Use a global variable HalpBuildType instead of a define when checking the BUILD (we don't recompile this code for SMP hal)
- Move registering IRQ2 out of the generic init code into HalInitializePICs
- Modify legacy HalpGetRootInterruptVector to use HalpIrqToVector and HalpVectorToIrql so it works with APIC, too
svn path=/trunk/; revision=53675
- Implement HalpApcInterruptHandler, fix HalpDispatchInterruptHandler
- Insert a read to the APIC version register in ApicGetCurrentIrql(). This fixes inconsistencies between the internal APIC state and register reads/writes.
- Remove old hacks in ApicGetCurrentIrql() and ApicSetCurrentIrql
- Fix HalpVectorToIrql()
- read/write cr8 for the value of the TPR on amd64 builds
- Fix amd64 build
svn path=/trunk/; revision=53673
