- Make NtUserSetCursor hide Cursor on hCursor = NULL
- Don't set the cursor pos if the cursor is hidden in IntMouseInput
- remove 2 useless ASSERTs
- Dereference old cursor- Make the screensaver lib hide the cursor directly after creating it (the window never recieves a WM_SETCURSOR)
partly fixes bug 2965
See issue #2965 for more details.
svn path=/trunk/; revision=32676
- This removes (hides?) the so-called "ResourceNeverExclusive" problem at the end of the 1st stage setup or during file copy operation. Also it makes file copying process (not only in the 1st stage) more stable.
- Cacheseg mapping region size enlarged to 256Mb.
See issue #2872 for more details.
svn path=/trunk/; revision=32675
- Start coding HalInitSystem.
- Implement HalRequestSoftwareInterrupt for the PL190 VIC. The interrupt fires! (This interrupt is responsible for forcing DPC delivery, which should also force thread scheduling, which should force the switch to the phase 1 thread)
svn path=/trunk/; revision=32674
They were confusingly coded to accept any flavor of PFN_TYPE, which resulted in at least one bug.
Constrained the calls to the MmRequest/ReleasePageMemoryConsumer and MmTrimUserMemory.
svn path=/trunk/; revision=32673
- The rest of Phase 0 initialization continues smoothly, we now reach the while(TRUE) loop at the end of KiSystemStartup!
- Phase 0 bring-up is complete: The phase 1 thread should now start (once thread scheduling works).
- Next steps: IRQLs, HAL Initialization (Timers and IRQs) to get the interval clock timer running for quantum end/scheduling/time accounting.
- After that: context switching code to be able to switch to the Phase 1 thread.
- Then: Phase 1 bring-up!
svn path=/trunk/; revision=32671
- Removed a bunch more i386-only exports from the ARM kernel.
- Implemented all the READ/WRITE_REGISTER* routines for ARM/PPC.
- Implement half of KiSoftwareInterruptException, which calls KiSoftwareInterruptHandler, which calls KiSystemService. We now reach the first kernel-mode system call! (ZwClose from PspInitPhase0).
- Reformat fastinterlck.c and change the way it's included per-architecture.
svn path=/trunk/; revision=32666
- Current status: we now make it all the way to the first system call at the end of Phase 0!
- We now make the IRQL routines modify the IRQL saved in the KPCR, to make some assertions work.
- Build mem.c and memgen.c from RTL in order to get non-optimized but portable Rtl*Memory routines and Rtl*Swap routines.
- Take the PPC non-optimized but portable Ex*Interlocked* routines and make them available for ARM as well. Play with the code a bit to get other routines in there too.
- Major TODO: Cleanup these routines, re-format them, make them compatible for all architectures, and later on, provided optimized ARM versions.
- Remove _all* _aull* MSVC-i386 helper exports from the kernel, as well as Exfi386* routines -- they're only for x86 kernels.
svn path=/trunk/; revision=32664
- Implement proper trap prolog/epilog code -- currently used and tested in the data abort handler. Currently hacked away some KTRAP_FRAME stuff on ARM.
- The data abort handler has a very rudimentary check to detect page faults and will call MmAccessFaults, this means we now support paged pool!
- We now succesfully go past MmInitSystem and go all the way until ObInitSystem (still in Phase 0).
svn path=/trunk/; revision=32659
- Rename and add two application compatibility flags to W32THREADINFO structure (one for ancient compat flags, and one for a bit more modern flags).
- Implement GetAppCompatFlags2() too.
svn path=/trunk/; revision=32657
- There is no reason to implement the Interlocked* APIs in assembly in the kernel -- just have them call the intrinsics.
- Also fix the way we were overloading the exported APIs, we now use the intrinsics all the time.
- Convert loader block address to virtual, and parse the addresses inside it and convert them to virtual too, after we don't use them in FreeLDR anymore -- the kernel will delete the p->v identity mapping, and eventually still need to touch the loader block.
- Implement MmGetPhysicalAddress and MiGetUserPageDirectoryCount for ARM.
- We now reach the point where we start initializing the boot drivers' memory information.
svn path=/trunk/; revision=32654
- Fix incorrect definition of ARM_CONTROL_REGISTER, which was stopping us from correctly enabling High Vectors.
- The RtlCaptureStackLimits and RtlWakeChainFrame routines in libsupp.c cannot possibly be portable across all architectures -- separated ARM versions in an arm directory.
- Setup the panic stack for abort/undefined exceptions, and the interrupt stack for FIQs.
- Implement support for exceptions! We can now display the address which caused a data abort, and begin handling exceptions.
- Implement all the HAL Spinlock/IRQL functions except KfRaise/LowerIrql which actually do the work.
- We're booting all the way to setting up the user_shared_data memory area.
svn path=/trunk/; revision=32653
- Implemented and defined the MMU-OS architecture for the ARM port. The details are too long for a commit message, but we have decided to replicate the x86 NT memory manager layout. We've defined a PTE_BASE at 0xC0000000 just like on x86, and we use a PDE_BASE at 0xC1000000. Unlike the x86, we can't use PDE-PTE self-mapping because ARM has different formats (and sizes!) for PDE vs PTEs! We emulate the behavior however (which adds a small performance hit) and the Mm porting is thus at least 10 times easier.
- Moved serial port to 0xE0000000 for now.
- We now parse the board memory map from u-boot.
- Added memory allocation code to FreeLDR -- we now build a full ARC memory map for the kernel.
- FreeLDR allocates page tables and sets up the initial support for our memory layout (see comments for some lengthier explenations)
- Allocations made by FreeLDR for loading ReactOS are now made from a "shared heap" page that's also marked in the memory map.
- Registry and NLS data are now being put into the loader block.
- We now create a loader entry for the kernel (but not anything else -- we'll have to parse the list properly later).
- Defined correct _HARDWARE_PTE_ARM and _MMPTE_HARDWARE for ARM.
- ARM_COARSE_PAGE_TABLE is now 4KB instead of 1KB, going against the architecture! We do this for proper OS support of the PTE_BASE.
- Fixed build due to KiSystemStartulReal change.
- Fixed a bug on the x86 build when creating memory allocation descriptors. Memory corruption could occur in certain scenarios.
- Implemented significant portions of the ARM memory manager code in the kernel:
- MmGetPageDirectory.
- MmDeletePageTable (for the kernel address space only).
- MmIsPagePresent (for the kernel address space only).
- MmCreateVirtualMappingForKernel.
- MmCreateVirtualMapping (calls MmCreateVirtualMappingUnsafe).
- MmCreateVirtualMappingUnsafe (for the kernel address space only).
- MmSetPageProtect (unused on ARM).
- MmCreateHyperspaceMapping.
- MmDeleteHyperspaceMapping.
- MmInitGlobalKernelPageDirectory.
- MmInitPageDirectoryMap.
- With the above, this means we now go well inside MmInit1: the PFN database is setup and works, memory areas are functional, and non-paged pool is fully working.
- We currently hit a data abort during paged pool setup -- this is to be expected, since we don't have any exception handlers yet. These are coming up next -- we have to start handling crashes (and page faults).
svn path=/trunk/; revision=32640
implemented command DRAFTMODE, FLUSHOUTPUT, SETCOLORTABLE for they are not longer supported in windows XP/2003
implemented command SETABORTPROC it is still stub in gdi32/misc/stubs.c
svn path=/trunk/; revision=32635
