mirror of
https://github.com/reactos/reactos.git
synced 2025-07-31 09:01:37 +00:00
- Implement IRQL functions for the PL190 VIC.
- Start coding HalInitSystem. - Implement HalRequestSoftwareInterrupt for the PL190 VIC. The interrupt fires! (This interrupt is responsible for forcing DPC delivery, which should also force thread scheduling, which should force the switch to the phase 1 thread) svn path=/trunk/; revision=32674
This commit is contained in:
ReactOS Portable Systems Group
parent
e2d5ba4e1f
commit
362ca1e480
3 changed files with 327 additions and 45 deletions
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@ -742,7 +742,7 @@ ArmSetupPageDirectory(VOID)
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ArmTable->Pte[0] = Pte;
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//
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// Map the page in MMIO space that contains the serial port into virtual memory
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// Map the page in MMIO space that contains the serial port and timers
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//
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Pte.L1.Section.BaseAddress = ArmBoardBlock->UartRegisterBase >> PDE_SHIFT;
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ArmTable->Pte[UART_VIRTUAL >> PDE_SHIFT] = Pte;
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@ -17,8 +17,10 @@
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#include <ndk/halfuncs.h>
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#include <ndk/iofuncs.h>
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#include <ndk/kdfuncs.h>
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#include <ndk/kefuncs.h>
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#include <internal/arm/ke.h>
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#include <internal/arm/intrin_i.h>
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#include <bugcodes.h>
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#define NDEBUG
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#include <debug.h>
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@ -32,6 +34,9 @@
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#undef KeRaiseIrql
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#undef KeReleaseSpinLock
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#define READ_REGISTER_ULONG(r) (*(volatile ULONG * const)(r))
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#define WRITE_REGISTER_ULONG(r, v) (*(volatile ULONG *)(r) = (v))
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/* DATA **********************************************************************/
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ULONG _KdComPortInUse = 0;
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@ -371,16 +376,210 @@ HalHandleNMI(
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UNIMPLEMENTED;
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}
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VOID
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NTAPI
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HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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PCHAR CommandLine;
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/* Make sure we have a loader block and command line */
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if ((LoaderBlock) && (LoaderBlock->LoadOptions))
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{
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/* Read the command line */
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CommandLine = LoaderBlock->LoadOptions;
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/* Check for initial breakpoint */
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if (strstr(CommandLine, "BREAK")) DbgBreakPoint();
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}
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}
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//
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// INTs on the Versatile:
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//
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// 0 WATCHDOG -> We use it for profiling
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// 1 SOFTWARE INTERRUPT -> We use it for APC delivery
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// 2 COMM RX -> We use it for DPC delivery
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// 3 COMM TX -> We use it for IPI delivery
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// 4 TIMER0/1 -> Use for Clock Interrupt.
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// 5+ XXX -> Mapped to to actual device
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//
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// So we have the following IRQL masks:
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// PASSIVE_LEVEL - 0xFFFFFFFF (enable all interrupts)
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// APC_LEVEL - 0xFFFFFFFD (disable interrupt 1)
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// DISPATCH_LEVEL - 0xFFFFFFF9 (disable interrupts 1, 2)
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// DEVICE_LEVEL_0 - 0xFFFFFFD9 (disable interrupts 1, 2, 5)
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// DEVICE_LEVEL_N - 0x19 (everything disabled except 0, 3, 4)
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// PROFILE_LEVEL - 0x18 (everything disabled except, 3, 4)
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// CLOCK_LEVEL - 0x10 (everything disabled except 4)
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// POWER_LEVEL, IPI_LEVEL, HIGH_LEVEL - 0x00 (everything disabled)
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ULONG HalpIrqlTable[] =
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{
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0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL
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0xFFFFFFFD, // IRQL 1 APC_LEVEL
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0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL
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0xFFFFFFD9, // IRQL 3
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0xFFFFFF99, // IRQL 4
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0xFFFFFF19, // IRQL 5
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0xFFFFFE19, // IRQL 6
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0xFFFFFC19, // IRQL 7
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0xFFFFF819, // IRQL 8
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0xFFFFF019, // IRQL 9
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0xFFFFE019, // IRQL 10
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0xFFFFC019, // IRQL 11
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0xFFFF8019, // IRQL 12
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0xFFFF0019, // IRQL 13
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0xFFFE0019, // IRQL 14
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0xFFFC0019, // IRQL 15
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0xFFF80019, // IRQL 16
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0xFFF00019, // IRQL 17
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0xFFE00019, // IRQL 18
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0xFFC00019, // IRQL 19
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0xFF800019, // IRQL 20
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0xFF000019, // IRQL 21
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0xFE000019, // IRQL 22
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0xFC000019, // IRQL 23
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0xF0000019, // IRQL 24
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0x80000019, // IRQL 25
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0x19, // IRQL 26
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0x18, // IRQL 27 PROFILE_LEVEL
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0x10, // IRQL 28 CLOCK2_LEVEL
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0x00, // IRQL 29 IPI_LEVEL
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0x00, // IRQL 30 POWER_LEVEL
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0x00, // IRQL 31 HIGH_LEVEL
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};
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VOID
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HalpStallInterrupt(VOID)
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{
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DPRINT1("STALL INTERRUPT!!!\n");
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while (TRUE);
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}
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VOID
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HalpInitializeInterrupts(VOID)
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{
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ULONG i;
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PKPCR Pcr = (PKPCR)KeGetPcr();
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//
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// Fill out the IRQL mappings
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//
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for (i = 0; i < (HIGH_LEVEL + 1); i++)
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{
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//
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// Save the valeue in the PCR
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//
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Pcr->IrqlTable[i] = HalpIrqlTable[i];
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}
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//
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// Setup the clock and profile interrupt
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//
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Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt;
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// Pcr->InterruptRoutine[PROFILE_LEVEL] = HalpCountInterrupt;
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}
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ULONG HalpCurrentTimeIncrement, HalpNextTimeIncrement, HalpNextIntervalCount;
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#define VICINTENABLE (PVOID)0xE0040010
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#define VICINTENCLEAR (PVOID)0xE0040014
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#define VICSOFTINT (PVOID)0xE0040018
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#define VICSOFTINTCLEAR (PVOID)0xE004001C
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/*
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* @implemented
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*/
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BOOLEAN
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NTAPI
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HalInitSystem(
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ULONG BootPhase,
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PLOADER_PARAMETER_BLOCK LoaderBlock)
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HalInitSystem(IN ULONG BootPhase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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UNIMPLEMENTED;
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return TRUE;
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PKPRCB Prcb = KeGetCurrentPrcb();
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//
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// Check the boot phase
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//
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if (!BootPhase)
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{
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//
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// Get command-line parameters
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//
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HalpGetParameters(LoaderBlock);
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#if DBG
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//
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// Checked HAL requires checked kernel
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//
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if (!(Prcb->BuildType & PRCB_BUILD_DEBUG))
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{
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//
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// No match, bugcheck
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//
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KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 1, 0);
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}
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#else
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//
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// Release build requires release HAL
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//
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if (Prcb->BuildType & PRCB_BUILD_DEBUG)
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{
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//
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// No match, bugcheck
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//
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KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0);
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}
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#endif
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#ifdef CONFIG_SMP
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//
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// SMP HAL requires SMP kernel
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//
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if (Prcb->BuildType & PRCB_BUILD_UNIPROCESSOR)
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{
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//
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// No match, bugcheck
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//
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KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0);
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}
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#endif
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//
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// Validate the PRCB
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//
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if (Prcb->MajorVersion != PRCB_MAJOR_VERSION)
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{
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//
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// Validation failed, bugcheck
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//
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KeBugCheckEx(MISMATCHED_HAL, 1, Prcb->MajorVersion, 1, 0);
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}
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//
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// Setup time increments to 10ms and 1ms
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//
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HalpCurrentTimeIncrement = 100000;
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HalpNextTimeIncrement = 100000;
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HalpNextIntervalCount = 0;
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KeSetTimeIncrement(100000, 10000);
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//
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// Initialize interrupts
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//
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HalpInitializeInterrupts();
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}
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else if (BootPhase == 1)
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{
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UNIMPLEMENTED;
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while (TRUE);
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}
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//
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// All done, return
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//
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return TRUE;
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}
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@ -484,10 +683,35 @@ HalRequestIpi(
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VOID
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FASTCALL
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HalRequestSoftwareInterrupt(
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KIRQL Request)
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HalRequestSoftwareInterrupt(IN KIRQL Request)
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{
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UNIMPLEMENTED;
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ULONG Interrupt = 0;
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//
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// Get the interrupt that maches this IRQL level
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//
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switch (Request)
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{
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case APC_LEVEL:
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Interrupt = 1 << 1;
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break;
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case DISPATCH_LEVEL:
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Interrupt = 1 << 2;
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break;
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default:
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ASSERT(FALSE);
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}
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//
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// Force a software interrupt
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//
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DPRINT1("About to force interrupt mask: %d\n", Interrupt);
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WRITE_REGISTER_ULONG(VICSOFTINT, Interrupt);
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}
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VOID FASTCALL
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@ -766,23 +990,79 @@ KeStallExecutionProcessor(
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VOID
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FASTCALL
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KfLowerIrql(
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KIRQL NewIrql)
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KfLowerIrql(IN KIRQL NewIrql)
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{
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KeGetPcr()->CurrentIrql = NewIrql;
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UNIMPLEMENTED;
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ULONG InterruptMask;
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PKPCR Pcr = (PKPCR)KeGetPcr();
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//
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// Validate the new IRQL
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//
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ASSERT(NewIrql <= Pcr->CurrentIrql);
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//
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// IRQLs are internally 8 bits
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//
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NewIrql &= 0xFF;
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//
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// Setup the interrupt mask for this IRQL
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//
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InterruptMask = KeGetPcr()->IrqlTable[NewIrql];
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DPRINT1("New IRQL: %d InterruptMask: %lx\n", NewIrql, InterruptMask);
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//
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// Clear interrupts associated to the old IRQL
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//
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WRITE_REGISTER_ULONG(VICINTENCLEAR, 0xFFFFFFFF);
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//
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// Set the new interrupt mask
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// PL190 VIC support only for now
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//
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WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
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//
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// Save the new IRQL
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//
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Pcr->CurrentIrql = NewIrql;
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}
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KIRQL
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FASTCALL
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KfRaiseIrql(
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KIRQL NewIrql)
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KfRaiseIrql(IN KIRQL NewIrql)
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{
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KIRQL OldIrql = KeGetPcr()->CurrentIrql;
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KeGetPcr()->CurrentIrql = NewIrql;
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UNIMPLEMENTED;
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KIRQL OldIrql;
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ULONG InterruptMask;
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PKPCR Pcr = (PKPCR)KeGetPcr();
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//
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// Save the current IRQL
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//
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OldIrql = Pcr->CurrentIrql;
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//
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// IRQLs are internally 8 bits
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//
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NewIrql &= 0xFF;
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//
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// Setup the interrupt mask for this IRQL
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//
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InterruptMask = KeGetPcr()->IrqlTable[NewIrql];
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DPRINT1("New IRQL: %d InterruptMask: %lx\n", NewIrql, InterruptMask);
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//ASSERT(NewIrql >= OldIrql);
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//
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// Set the new interrupt mask
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// PL190 VIC support only for now
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//
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WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
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//
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// Save the new IRQL
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//
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Pcr->CurrentIrql = NewIrql;
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return OldIrql;
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}
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@ -915,28 +1195,28 @@ WRITE_PORT_USHORT(
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KIRQL
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KeSwapIrql(IN KIRQL Irql)
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{
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KIRQL OldIrql = KeGetPcr()->CurrentIrql;
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KeGetPcr()->CurrentIrql = Irql;
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UNIMPLEMENTED;
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return OldIrql;
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//
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// Call the generic routine
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//
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return KfRaiseIrql(Irql);
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}
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KIRQL
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KeRaiseIrqlToDpcLevel(VOID)
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{
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KIRQL OldIrql = KeGetPcr()->CurrentIrql;
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KeGetPcr()->CurrentIrql = SYNCH_LEVEL;
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UNIMPLEMENTED;
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return OldIrql;
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//
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// Call the generic routine
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//
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return KfRaiseIrql(DISPATCH_LEVEL);
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}
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KIRQL
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KeRaiseIrqlToSynchLevel(VOID)
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{
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KIRQL OldIrql = KeGetPcr()->CurrentIrql;
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KeGetPcr()->CurrentIrql = SYNCH_LEVEL;
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UNIMPLEMENTED;
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return OldIrql;
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//
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// Call the generic routine
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//
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return KfRaiseIrql(DISPATCH_LEVEL);
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}
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BOOLEAN HalpProcessorIdentified;
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@ -1136,7 +1416,7 @@ KeAcquireInStackQueuedSpinLockRaiseToSynch(IN PKSPIN_LOCK SpinLock,
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IN PKLOCK_QUEUE_HANDLE LockHandle)
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{
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/* Simply raise to synch */
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LockHandle->OldIrql = KfRaiseIrql(SYNCH_LEVEL);
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LockHandle->OldIrql = KfRaiseIrql(DISPATCH_LEVEL);
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}
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/*
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@ -4,15 +4,17 @@
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//
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// IRQLs
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//
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#define PASSIVE_LEVEL 0
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#define LOW_LEVEL 0
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#define APC_LEVEL 1
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#define DISPATCH_LEVEL 2
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#define IPI_LEVEL 7
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#define POWER_LEVEL 7
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#define PROFILE_LEVEL 8
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#define HIGH_LEVEL 8
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#define SYNCH_LEVEL (IPI_LEVEL - 1)
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#define PASSIVE_LEVEL 0
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#define LOW_LEVEL 0
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#define APC_LEVEL 1
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#define DISPATCH_LEVEL 2
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#define SYNCH_LEVEL DISPATCH_LEVEL
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#define PROFILE_LEVEL 27
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#define CLOCK1_LEVEL 28
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#define CLOCK2_LEVEL 28
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#define IPI_LEVEL 29
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#define POWER_LEVEL 30
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#define HIGH_LEVEL 31
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//
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// FIXME: mmtypes.h?
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@ -83,8 +85,8 @@ typedef struct _KPCR
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PVOID InstructionBusError;
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ULONG CachePolicy;
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ULONG AlignedCachePolicy;
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UCHAR IrqlMask[64];
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UCHAR IrqlTable[64];
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// UCHAR IrqlMask[64];
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ULONG IrqlTable[HIGH_LEVEL + 1];
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UCHAR CurrentIrql;
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KAFFINITY SetMember;
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struct _KTHREAD *CurrentThread;
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