Implement lazy irql for APIC. This is useful for VMs, since APIC usually has high overhead due to the need of invoking the hypervisor on every irql raise and lower. With lazy irql we avoid that until absolutely neccessary. Note that we misuse the PCR's IRR field to save the current hardware irql. Its a huge performance boost (some parts take half the time), making APIC performance close to PIC performance on VBox. This is something that Windows doesn't have :)
svn path=/trunk/; revision=53695
- Create a volatile device tree during 1st stage so the new HAL that's loaded in 2nd stage can do proper enumeration without phantom devices from the old HAL
svn path=/trunk/; revision=53694
- Fix incorrect loop boundaries in the ARM version of MmCreateProcessAddressSpace. Spotted by Vincenzo Cotugno and cppcheck
- Correct outdated wineimport.cmd URL in README.WINE
- Assorted spelling and readability fixes
svn path=/trunk/; revision=53688
- Add support for guarded allocations, that can be used to detect buffer overruns
- Add GuardedMemory example test
- Add MmSection test with some basic parameter checks for MmCreateSection
- Fix some x64 build problems
- Update readme
svn path=/trunk/; revision=53687
- Add optional asynchronous io code for service control pipes. This is disabled by default due to bugs in NPFS.
- Read service pipe timeout value from the registry.
svn path=/trunk/; revision=53686
- End the interrupt in HalpApcInterruptHandler and HalpDispatchInterruptHandler before calling the kernel, otherwise we would be stuck at high processor irql
- Improve HalEnableSystemInterrupt
- disable interrupts in HalpInitializeClock
=> APIC hal boots to desktop!
svn path=/trunk/; revision=53685
The handlers for unexpected interrupts that we generate from asm macros use a push instruction with an 8 bit operand to push the interrupt number on the stack. Now the 8 bit push has the unfortunate behaviour of sign extending to 32 bit. But since the assembler is smart (or at least thinks so) it will not generate such a push instruction for values larger than 0x7f. This resulted in 7 bytes long stubs in the range of 0x30 .. 0x7f and 10 bytes long stubs after that. To fix this 128 is substracted from the value and later readded in the common code path. A second issue arose, because the assembler would start to use 8 bit relative short jumps as soon as the target was less than 127 bytes away, which happened for some of the higher interrupts, which then had a smaller stub then the others. Fix this by moving the stubs up in the code further away from the target label, so that always 32bit relative jumps will be used. These problems didn't show up so far, since we used the PIC and interrupts in the range of 0x30 .. 0x40 and the code that relied on the stubs all having the same length was working well. This changes with an APIC based hal, where interrupts of much higher number are likely to be used.
svn path=/trunk/; revision=53679
- Use a global variable HalpBuildType instead of a define when checking the BUILD (we don't recompile this code for SMP hal)
- Move registering IRQ2 out of the generic init code into HalInitializePICs
- Modify legacy HalpGetRootInterruptVector to use HalpIrqToVector and HalpVectorToIrql so it works with APIC, too
svn path=/trunk/; revision=53675
- Implement HalpApcInterruptHandler, fix HalpDispatchInterruptHandler
- Insert a read to the APIC version register in ApicGetCurrentIrql(). This fixes inconsistencies between the internal APIC state and register reads/writes.
- Remove old hacks in ApicGetCurrentIrql() and ApicSetCurrentIrql
- Fix HalpVectorToIrql()
- read/write cr8 for the value of the TPR on amd64 builds
- Fix amd64 build
svn path=/trunk/; revision=53673
- Skip the remaining tests that result in assertions
- Hide KeProcessor test, as it takes very long
svn path=/branches/GSoC_2011/KMTestSuite/; revision=53669
Add a hack to work around a bug in VBox: The APIC emulation requires an iret instruction following closely after writing the EOI register. Since we return from kernel mode traps with a jmp (yes you can return from an interrupt with a jmp!) the EOI is never triggered, making VBox believe we are still serving the interrupt and keeping the PPR on high level, preventing following interrupts. A small asm stub now does the work of both writing the EOI and doing an iret.
svn path=/trunk/; revision=53665
- Add a hack to ApicGetCurrentIrql and ApicSetCurrentIrql to work around a VBox bug
- call KeSetTimeIncrement after initializing the rtc clock
- calculate TSC frequency from the samples
- Fix a bug in KeStallExecutionProcessor
svn path=/trunk/; revision=53658
- Rename gQueueKeyStateTable to gKeyStateTable as it has nothing to do with msg queues. They have their own table
- Use KS_*_BIT defines instead of magic values
svn path=/trunk/; revision=53655
* Reintegrate the c++ shell32 branch. Exemplary team-work.. kudos !
* Better code quality, more tests run with less failures... and more.
* Dedicated to everyone who helped ;)
svn path=/trunk/; revision=53653
[FORMATTING]
- Second wave of formatting. At least now we won't have any tabs and spaces mixed in.
svn path=/branches/shell32_new-bringup/; revision=53651
- Fix bug 6336 of shell32_new. The bug was caused by not properly verifying the return value of ShellExecuteExW.
[FORMATTING]
- First wave of accidental formatting (sorry again about mixing code and formatting heh).
svn path=/branches/shell32_new-bringup/; revision=53650
- Start a new device manager to test the reactos ATL code.
- Also, the old one sucks big time and was quickly hacked together.
svn path=/trunk/; revision=53648
