a5764f8181
the access functions for pci config space in config mode #1 used to set bit 0 in the register offset if the access was to a device on any bus different from 0. it is completely unclear why this was done and i can't find any documentation on this. but for sure, this breaks all pci config spacess access to pci devices behind a bridge on qemu. with -trace pci* it was discovered that all config space register offsets on devies behind pci brige where off by one. on real hardware, setting bit 0 in the offset doesnt appear to be an issue. thanks mischief for reporting and providing a qemu demo configuration to reproduce the problem. |
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