pc, pc64: remove mystery "type" bits in pcicfgrw*raw() (fixes qemu, thanks mischief)

the access functions for pci config space in config mode #1
used to set bit 0 in the register offset if the access was
to a device on any bus different from 0.

it is completely unclear why this was done and i can't find
any documentation on this.

but for sure, this breaks all pci config spacess access to
pci devices behind a bridge on qemu. with -trace pci* it
was discovered that all config space register offsets on
devies behind pci brige where off by one.

on real hardware, setting bit 0 in the offset doesnt appear
to be an issue.

thanks mischief for reporting and providing a qemu demo
configuration to reproduce the problem.
This commit is contained in:
cinap_lenrek 2020-10-18 23:39:07 +02:00
parent d1604b5f9c
commit a5764f8181

View file

@ -36,17 +36,13 @@ int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
static int
pcicfgrw8raw(int tbdf, int rno, int data, int read)
{
int o, type;
int o;
if(BUSBNO(tbdf))
type = 0x01;
else
type = 0x00;
switch(pcicfgmode){
case 1:
o = rno & 0x03;
rno &= ~0x03;
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
if(read)
data = inb(PciDATA+o);
else
@ -72,17 +68,13 @@ pcicfgrw8raw(int tbdf, int rno, int data, int read)
static int
pcicfgrw16raw(int tbdf, int rno, int data, int read)
{
int o, type;
int o;
if(BUSBNO(tbdf))
type = 0x01;
else
type = 0x00;
switch(pcicfgmode){
case 1:
o = rno & 0x02;
rno &= ~0x03;
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
if(read)
data = ins(PciDATA+o);
else
@ -108,16 +100,10 @@ pcicfgrw16raw(int tbdf, int rno, int data, int read)
static int
pcicfgrw32raw(int tbdf, int rno, int data, int read)
{
int type;
if(BUSBNO(tbdf))
type = 0x01;
else
type = 0x00;
switch(pcicfgmode){
case 1:
rno &= ~0x03;
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
if(read)
data = inl(PciDATA);
else