pc, pc64: remove mystery "type" bits in pcicfgrw*raw() (fixes qemu, thanks mischief)
the access functions for pci config space in config mode #1 used to set bit 0 in the register offset if the access was to a device on any bus different from 0. it is completely unclear why this was done and i can't find any documentation on this. but for sure, this breaks all pci config spacess access to pci devices behind a bridge on qemu. with -trace pci* it was discovered that all config space register offsets on devies behind pci brige where off by one. on real hardware, setting bit 0 in the offset doesnt appear to be an issue. thanks mischief for reporting and providing a qemu demo configuration to reproduce the problem.
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1 changed files with 5 additions and 19 deletions
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@ -36,17 +36,13 @@ int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
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static int
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pcicfgrw8raw(int tbdf, int rno, int data, int read)
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{
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int o, type;
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int o;
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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switch(pcicfgmode){
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case 1:
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o = rno & 0x03;
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rno &= ~0x03;
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
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if(read)
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data = inb(PciDATA+o);
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else
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@ -72,17 +68,13 @@ pcicfgrw8raw(int tbdf, int rno, int data, int read)
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static int
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pcicfgrw16raw(int tbdf, int rno, int data, int read)
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{
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int o, type;
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int o;
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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switch(pcicfgmode){
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case 1:
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o = rno & 0x02;
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rno &= ~0x03;
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
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if(read)
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data = ins(PciDATA+o);
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else
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@ -108,16 +100,10 @@ pcicfgrw16raw(int tbdf, int rno, int data, int read)
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static int
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pcicfgrw32raw(int tbdf, int rno, int data, int read)
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{
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int type;
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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switch(pcicfgmode){
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case 1:
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rno &= ~0x03;
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno);
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if(read)
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data = inl(PciDATA);
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else
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