574 lines
12 KiB
ArmAsm
574 lines
12 KiB
ArmAsm
/*
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* ti omap3530 SoC machine assist
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* arm cortex-a8 processor
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*
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* loader uses R11 as scratch.
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* R9 and R10 are used for `extern register' variables.
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*
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* ARM v7 arch. ref. man. §B1.3.3 that we don't need barriers
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* around moves to CPSR.
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*/
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#include "arm.s"
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/*
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* MCR and MRC are counter-intuitively named.
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* MCR coproc, opcode1, Rd, CRn, CRm[, opcode2] # arm -> coproc
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* MRC coproc, opcode1, Rd, CRn, CRm[, opcode2] # coproc -> arm
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*/
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/*
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* Entered here from Das U-Boot or another Plan 9 kernel with MMU disabled.
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* Until the MMU is enabled it is OK to call functions provided
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* they are within ±32MiB relative and do not require any
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* local variables or more than one argument (i.e. there is
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* no stack).
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*/
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TEXT _start(SB), 1, $-4
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MOVW $setR12(SB), R12 /* load the SB */
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SUB $KZERO, R12
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ADD $PHYSDRAM, R12
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/* SVC mode, interrupts disabled */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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BARRIERS
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DELAY(printloopret, 1)
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WAVE('\r')
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DELAY(printloopnl, 1)
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WAVE('\n')
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/*
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* work around errata
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $(CpACissue1|CpACldstissue1), R1 /* fight omap35x errata 3.1.1.9 */
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ORR $CpACibe, R1 /* enable cp15 invalidate */
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ORR $CpACl1pe, R1 /* enable l1 parity checking */
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ORR $CpCalign, R1 /* catch alignment errors */
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BIC $CpACasa, R1 /* no speculative accesses */
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/* go faster with fewer restrictions */
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BIC $(CpACcachenopipe|CpACcp15serial|CpACcp15waitidle|CpACcp15pipeflush), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ISB
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MRC CpSC, 1, R1, C(CpCLD), C(CpCLDl2), CpCLDl2aux
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ORR $CpCl2nowralloc, R1 /* fight cortex errata 460075 */
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ORR $(CpCl2ecc|CpCl2eccparity), R1
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#ifdef TEDIUM
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/*
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* I don't know why this clobbers the system, but I'm tired
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* of arguing with this fussy processor. To hell with it.
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*/
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MCR CpSC, 1, R1, C(CpCLD), C(CpCLDl2), CpCLDl2aux
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ISB
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#endif
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DELAY(printloops, 1)
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WAVE('P')
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/*
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* disable the MMU & caches
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCmmu), R1
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ORR $CpCsbo, R1
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BIC $CpCsbz, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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ISB
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BIC $CpACl2en, R1 /* turn l2 cache off */
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ISB
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WAVE('l')
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DELAY(printloop3, 1)
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WAVE('a')
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/* clear Mach */
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MOVW $PADDR(MACHADDR), R4 /* address of Mach */
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MOVW $0, R0
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_machZ:
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MOVW R0, (R4)
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ADD $4, R4
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CMP.S $PADDR(L1+L1X(0)), R4 /* end at top-level page table */
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BNE _machZ
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/*
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* set up the MMU page table
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*/
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WAVE('n')
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/* clear all PTEs first, to provide a default */
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// MOVW $PADDR(L1+L1X(0)), R4 /* address of PTE for 0 */
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_ptenv0:
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ZEROPTE()
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CMP.S $PADDR(L1+16*KiB), R4
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BNE _ptenv0
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DELAY(printloop4, 2)
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WAVE(' ')
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/*
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* set up double map of PHYSDRAM, KZERO to PHYSDRAM for first few MBs,
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* but only if KZERO and PHYSDRAM differ.
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*/
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3 /* pa */
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CMP $KZERO, R3
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BEQ no2map
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MOVW $PADDR(L1+L1X(PHYSDRAM)), R4 /* address of PTE for PHYSDRAM */
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MOVW $DOUBLEMAPMBS, R5
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_ptdbl:
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FILLPTE()
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SUB.S $1, R5
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BNE _ptdbl
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no2map:
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/*
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* back up and fill in PTEs for memory at KZERO.
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* beagle has 1 bank of 256MB of SDRAM at PHYSDRAM;
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* igepv2 has 1 bank of 512MB at PHYSDRAM.
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* Map the maximum (512MB).
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*/
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WAVE('9')
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3
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MOVW $PADDR(L1+L1X(KZERO)), R4 /* start with PTE for KZERO */
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MOVW $512, R5 /* inner loop count (MBs) */
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_ptekrw: /* set PTEs */
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FILLPTE()
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SUB.S $1, R5 /* decrement inner loop count */
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BNE _ptekrw
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/*
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* back up and fill in PTEs for MMIO
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* stop somewhere after uarts
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*/
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WAVE(' ')
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MOVW $PTEIO, R2 /* PTE bits */
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MOVW $PHYSIO, R3
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MOVW $PADDR(L1+L1X(VIRTIO)), R4 /* start with PTE for VIRTIO */
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_ptenv2:
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FILLPTE()
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CMP.S $PADDR(L1+L1X(PHYSIOEND)), R4
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BNE _ptenv2
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/* mmu.c sets up the trap vectors later */
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/*
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* set up a temporary stack; avoid data & bss segments
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*/
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MOVW $(PHYSDRAM | (128*1024*1024)), R13
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/* invalidate caches */
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BL cachedinv(SB)
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MOVW $KZERO, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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ISB
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
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BARRIERS
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WAVE('f')
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/*
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* turn caches on
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*/
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ORR $CpACl2en, R1 /* turn l2 cache on */
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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ORR $(CpCdcache|CpCicache), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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WAVE('r')
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/* set the domain access control */
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MOVW $Client, R0
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BL dacput(SB)
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DELAY(printloop5, 2)
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WAVE('o')
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/* set the translation table base */
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MOVW $PADDR(L1), R0
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BL ttbput(SB)
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MOVW $0, R0
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BL pidput(SB) /* paranoia */
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WAVE('m')
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/*
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* the little dance to turn the MMU on
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*/
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BL cacheuwbinv(SB)
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BL mmuinvalidate(SB)
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BL mmuenable(SB)
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WAVE(' ')
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/* warp the PC into the virtual map */
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MOVW $KZERO, R0
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BL _r15warp(SB)
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/*
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* now running at KZERO+something!
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*/
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MOVW $setR12(SB), R12 /* reload the SB */
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/*
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* set up temporary stack again, in case we've just switched
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* to a new register set.
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*/
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MOVW $(KZERO|(128*1024*1024)), R13
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/* can now execute arbitrary C code */
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BL cacheuwbinv(SB)
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WAVE('B')
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MOVW $PHYSDRAM, R3 /* pa */
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CMP $KZERO, R3
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BEQ no2unmap
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/* undo double map of PHYSDRAM, KZERO & first few MBs */
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MOVW $(L1+L1X(PHYSDRAM)), R4 /* addr. of PTE for PHYSDRAM */
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MOVW $0, R0
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MOVW $DOUBLEMAPMBS, R5
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_ptudbl:
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ZEROPTE()
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SUB.S $1, R5
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BNE _ptudbl
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no2unmap:
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BARRIERS
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MOVW $KZERO, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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#ifdef HIGH_SECURITY /* i.e., not GP omap */
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/* hack: set `secure monitor' vector base addr for cortex */
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// MOVW $HVECTORS, R0
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MOVW $PADDR(L1), R0
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SUB $(MACHSIZE+(2*1024)), R0
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MCR CpSC, 0, R0, C(CpVECS), C(CpVECSbase), CpVECSmon
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ISB
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#endif
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/*
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* call main in C
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* pass Mach to main and set up the stack in it
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*/
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MOVW $(MACHADDR), R0 /* Mach */
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MOVW R0, R13
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ADD $(MACHSIZE), R13 /* stack pointer */
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SUB $4, R13 /* space for link register */
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MOVW R0, R10 /* m = MACHADDR */
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WAVE('e')
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BL main(SB) /* void main(Mach*) */
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/*FALLTHROUGH*/
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/*
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* reset the system
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*/
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TEXT _reset(SB), 1, $-4
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R0
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MOVW R0, CPSR
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BARRIERS
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DELAY(printloopr, 2)
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WAVE('!')
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WAVE('r')
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WAVE('e')
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WAVE('s')
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WAVE('e')
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WAVE('t')
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WAVE('!')
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WAVE('\r')
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WAVE('\n')
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/* turn the caches off */
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BL cacheuwbinv(SB)
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MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCicache|CpCdcache|CpCalign), R0
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ORR $CpCsw, R0 /* enable SWP */
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MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/* redo double map of PHYSDRAM, KZERO & first few MBs */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3 /* pa */
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MOVW $(L1+L1X(PHYSDRAM)), R4 /* address of PHYSDRAM's PTE */
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MOVW $DOUBLEMAPMBS, R5
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_ptrdbl:
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FILLPTE()
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SUB.S $1, R5
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BNE _ptrdbl
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MOVW $PHYSDRAM, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* turn the MMU off */
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MOVW $PHYSDRAM, R0
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BL _r15warp(SB)
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BL mmuinvalidate(SB)
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BL mmudisable(SB)
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/* set new reset vector */
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MOVW $HVECTORS, R2
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MOVW $0xe59ff018, R3 /* MOVW 0x18(R15), R15 */
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MOVW R3, (R2)
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BARRIERS
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// MOVW $PHYSFLASH, R3 /* TODO */
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// MOVW R3, 0x20(R2) /* where $0xe59ff018 jumps to */
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/* ...and jump to it */
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// MOVW R2, R15 /* software reboot */
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_limbo: /* should not get here... */
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BL idlehands(SB)
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B _limbo /* ... and can't get out */
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BL _div(SB) /* hack to load _div, etc. */
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TEXT _r15warp(SB), 1, $-4
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BIC $KSEGM, R14 /* link reg, will become PC */
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ORR R0, R14
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BIC $KSEGM, R13 /* SP too */
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ORR R0, R13
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RET
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/*
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* `single-element' cache operations.
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* in arm arch v7, they operate on all cache levels, so separate
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* l2 functions are unnecessary.
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*/
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TEXT cachedwbse(SB), $-4 /* D writeback SE */
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MOVW R0, R2
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MOVW CPSR, R3
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CPSID /* splhi */
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BARRIERS /* force outstanding stores to cache */
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MOVW R2, R0
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MOVW 4(FP), R1
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ADD R0, R1 /* R1 is end address */
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BIC $(CACHELINESZ-1), R0 /* cache line start */
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_dwbse:
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEse
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/* can't have a BARRIER here since it zeroes R0 */
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ADD $CACHELINESZ, R0
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CMP.S R0, R1
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BGT _dwbse
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B _wait
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TEXT cachedwbinvse(SB), $-4 /* D writeback+invalidate SE */
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MOVW R0, R2
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MOVW CPSR, R3
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CPSID /* splhi */
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BARRIERS /* force outstanding stores to cache */
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MOVW R2, R0
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MOVW 4(FP), R1
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ADD R0, R1 /* R1 is end address */
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BIC $(CACHELINESZ-1), R0 /* cache line start */
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_dwbinvse:
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEse
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/* can't have a BARRIER here since it zeroes R0 */
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ADD $CACHELINESZ, R0
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CMP.S R0, R1
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BGT _dwbinvse
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_wait: /* drain write buffer */
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BARRIERS
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
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ISB
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MOVW R3, CPSR /* splx */
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RET
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TEXT cachedinvse(SB), $-4 /* D invalidate SE */
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MOVW R0, R2
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MOVW CPSR, R3
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CPSID /* splhi */
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BARRIERS /* force outstanding stores to cache */
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MOVW R2, R0
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MOVW 4(FP), R1
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ADD R0, R1 /* R1 is end address */
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BIC $(CACHELINESZ-1), R0 /* cache line start */
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_dinvse:
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEse
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/* can't have a BARRIER here since it zeroes R0 */
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ADD $CACHELINESZ, R0
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CMP.S R0, R1
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BGT _dinvse
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B _wait
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/*
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* enable mmu and high vectors
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*/
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TEXT mmuenable(SB), 1, $-4
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MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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ORR $(CpChv|CpCmmu), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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RET
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TEXT mmudisable(SB), 1, $-4
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MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpChv|CpCmmu), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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RET
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/*
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* If one of these MCR instructions crashes or hangs the machine,
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* check your Level 1 page table (at TTB) closely.
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*/
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TEXT mmuinvalidate(SB), $-4 /* invalidate all */
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MOVW CPSR, R2
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CPSID /* interrupts off */
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BARRIERS
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MOVW PC, R0 /* some valid virtual address */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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MOVW R2, CPSR /* interrupts restored */
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RET
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TEXT mmuinvalidateaddr(SB), $-4 /* invalidate single entry */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
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BARRIERS
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RET
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TEXT cpidget(SB), 1, $-4 /* main ID */
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MRC CpSC, 0, R0, C(CpID), C(0), CpIDid
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RET
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TEXT cpctget(SB), 1, $-4 /* cache type */
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MRC CpSC, 0, R0, C(CpID), C(0), CpIDct
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RET
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TEXT controlget(SB), 1, $-4 /* control */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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RET
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TEXT ttbget(SB), 1, $-4 /* translation table base */
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MRC CpSC, 0, R0, C(CpTTB), C(0), CpTTB0
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RET
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TEXT ttbput(SB), 1, $-4 /* translation table base */
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MCR CpSC, 0, R0, C(CpTTB), C(0), CpTTB0
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MCR CpSC, 0, R0, C(CpTTB), C(0), CpTTB1 /* cortex has two */
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ISB
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RET
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TEXT dacget(SB), 1, $-4 /* domain access control */
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MRC CpSC, 0, R0, C(CpDAC), C(0)
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RET
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TEXT dacput(SB), 1, $-4 /* domain access control */
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MCR CpSC, 0, R0, C(CpDAC), C(0)
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ISB
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RET
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TEXT fsrget(SB), 1, $-4 /* data fault status */
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MRC CpSC, 0, R0, C(CpFSR), C(0), CpDFSR
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RET
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TEXT ifsrget(SB), 1, $-4 /* instruction fault status */
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MRC CpSC, 0, R0, C(CpFSR), C(0), CpIFSR
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RET
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TEXT farget(SB), 1, $-4 /* fault address */
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MRC CpSC, 0, R0, C(CpFAR), C(0x0)
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RET
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TEXT getpsr(SB), 1, $-4
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MOVW CPSR, R0
|
|
RET
|
|
|
|
TEXT getscr(SB), 1, $-4
|
|
MRC CpSC, 0, R0, C(CpCONTROL), C(CpCONTROLscr), CpSCRscr
|
|
RET
|
|
|
|
TEXT pidget(SB), 1, $-4 /* address translation pid */
|
|
MRC CpSC, 0, R0, C(CpPID), C(0x0)
|
|
RET
|
|
|
|
TEXT pidput(SB), 1, $-4 /* address translation pid */
|
|
MCR CpSC, 0, R0, C(CpPID), C(0x0)
|
|
ISB
|
|
RET
|
|
|
|
TEXT splhi(SB), 1, $-4
|
|
MOVW CPSR, R0
|
|
CPSID /* turn off interrupts */
|
|
|
|
MOVW $(MACHADDR+4), R2 /* save caller pc in Mach */
|
|
MOVW R14, 0(R2)
|
|
RET
|
|
|
|
TEXT spllo(SB), 1, $-4 /* start marker for devkprof.c */
|
|
MOVW CPSR, R0
|
|
CPSIE
|
|
RET
|
|
|
|
TEXT splx(SB), 1, $-4
|
|
MOVW $(MACHADDR+0x04), R2 /* save caller pc in Mach */
|
|
MOVW R14, 0(R2)
|
|
|
|
MOVW CPSR, R3
|
|
MOVW R0, CPSR /* reset interrupt level */
|
|
MOVW R3, R0 /* must return old CPSR */
|
|
RET
|
|
|
|
TEXT spldone(SB), 1, $0 /* end marker for devkprof.c */
|
|
RET
|
|
|
|
TEXT islo(SB), 1, $-4
|
|
MOVW CPSR, R0
|
|
AND $(PsrDirq), R0
|
|
EOR $(PsrDirq), R0
|
|
RET
|
|
|
|
TEXT tas(SB), $-4
|
|
TEXT _tas(SB), $-4
|
|
MOVW R0,R1
|
|
MOVW $1,R0
|
|
SWPW R0,(R1) /* fix: deprecated in armv7 */
|
|
RET
|
|
|
|
TEXT clz(SB), $-4
|
|
CLZ(0, 0) /* 0 is R0 */
|
|
RET
|
|
|
|
TEXT setlabel(SB), 1, $-4
|
|
MOVW R13, 0(R0) /* sp */
|
|
MOVW R14, 4(R0) /* pc */
|
|
MOVW $0, R0
|
|
RET
|
|
|
|
TEXT gotolabel(SB), 1, $-4
|
|
MOVW 0(R0), R13 /* sp */
|
|
MOVW 4(R0), R14 /* pc */
|
|
MOVW $1, R0
|
|
RET
|
|
|
|
TEXT getcallerpc(SB), 1, $-4
|
|
MOVW 0(R13), R0
|
|
RET
|
|
|
|
TEXT idlehands(SB), $-4
|
|
BARRIERS
|
|
WFI
|
|
RET
|
|
|
|
TEXT coherence(SB), $-4
|
|
BARRIERS
|
|
RET
|
|
|
|
#include "cache.v7.s"
|