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omap: fix breakpoint instruction trap handling (from sources)

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This commit is contained in:
cinap_lenrek 2013-01-25 14:48:57 +01:00
parent 358f72266a
commit 180e04ee41
4 changed files with 30 additions and 3 deletions
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6
sys/src/9/omap/arm.h
View file

@ -33,6 +33,12 @@
#define CpDFP 11 /* double FP */
#define CpSC 15 /* System Control */
/*
* CpFSR op1==0, Crm==0 opcode 2 values.
*/
#define CpDFSR 0 /* data fault status */
#define CpIFSR 1 /* instruction fault status */
/*
* Primary (CRn) CpSC registers.
*/

1
sys/src/9/omap/fns.h
View file

@ -50,6 +50,7 @@ extern u32int fsrget(void);
extern u32int getscr(void);
extern u32int getpsr(void);
extern ulong getwayssets(void);
extern u32int ifsrget(void);
extern void intrsoff(void);
extern int isaconfig(char*, int, ISAConf*);
extern int isdmadone(int);

8
sys/src/9/omap/l.s
View file

@ -474,10 +474,14 @@ TEXT dacput(SB), 1, $-4 /* domain access control */
ISB
RET
TEXT fsrget(SB), 1, $-4 /* fault status */
MRC CpSC, 0, R0, C(CpFSR), C(0)
TEXT fsrget(SB), 1, $-4 /* data fault status */
MRC CpSC, 0, R0, C(CpFSR), C(0), CpDFSR
RET
TEXT ifsrget(SB), 1, $-4 /* instruction fault status */
MRC CpSC, 0, R0, C(CpFSR), C(0), CpIFSR
RET
TEXT farget(SB), 1, $-4 /* fault address */
MRC CpSC, 0, R0, C(CpFAR), C(0x0)
RET

18
sys/src/9/omap/trap.c
View file

@ -493,7 +493,23 @@ trap(Ureg *ureg)
break;
case PsrMabt: /* prefetch fault */
ldrexvalid = 0;
faultarm(ureg, ureg->pc, user, 1);
x = ifsrget();
fsr = (x>>7) & 0x8 | x & 0x7;
switch(fsr){
case 0x02: /* instruction debug event (BKPT) */
if(user){
snprint(buf, sizeof buf, "sys: breakpoint");
postnote(up, 1, buf, NDebug);
}else{
iprint("kernel bkpt: pc %#lux inst %#ux\n",
ureg->pc, *(u32int*)ureg->pc);
panic("kernel bkpt");
}
break;
default:
faultarm(ureg, ureg->pc, user, 1);
break;
}
break;
case PsrMabt+1: /* data fault */
ldrexvalid = 0;