5608be398e
- clean dcache before turning off caches and mmu (rebootcode.s) - use WFE and inter-core mailboxes for cpu startup (rebootcode.s) - disable SMP during dcache invalidation before enabling caches and mmu (in armv7.s)
93 lines
1.9 KiB
ArmAsm
93 lines
1.9 KiB
ArmAsm
/*
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* armv6/armv7 reboot code
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*/
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#include "arm.s"
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#define WFI WORD $0xe320f003 /* wait for interrupt */
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#define WFE WORD $0xe320f002 /* wait for event */
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TEXT main(SB), 1, $-4
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MOVW $setR12(SB), R12
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MOVW R0, entry+0(FP)
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CMP $0, R0
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BEQ shutdown
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MOVW entry+0(FP), R8
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MOVW code+4(FP), R9
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MOVW size+8(FP), R6
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/* round to words */
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BIC $3, R8
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BIC $3, R9
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ADD $3, R6
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BIC $3, R6
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memloop:
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MOVM.IA.W (R9), [R1]
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MOVM.IA.W [R1], (R8)
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SUB.S $4, R6
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BNE memloop
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shutdown:
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/* clean dcache using appropriate code for armv6 or armv7 */
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MRC CpSC, 0, R1, C(CpID), C(CpIDfeat), 7 /* Memory Model Feature Register 3 */
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TST $0xF, R1 /* hierarchical cache maintenance? */
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BNE l2wb
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DSB
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEall
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B l2wbx
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l2wb:
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BL cachedwb(SB)
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BL l2cacheuwb(SB)
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l2wbx:
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/* load entry before turning off mmu */
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MOVW entry+0(FP), R8
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/* disable caches */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCpredict), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/* invalidate icache */
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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BARRIERS
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/* turn off mmu */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $CpCmmu, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/* turn SMP off */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BIC $CpACsmp, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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ISB
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DSB
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/* have entry? */
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CMP $0, R8
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BNE bootcpu
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/* other cpus wait for inter processor interrupt */
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CPUID(R2)
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dowfi:
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WFE /* wait for event signal */
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MOVW $0x400000CC, R1 /* inter-core .startcpu mailboxes */
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ADD R2<<4, R1 /* mailbox for this core */
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MOVW 0(R1), R8 /* content of mailbox */
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CMP $0, R8
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BEQ dowfi /* if zero, wait again */
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bootcpu:
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BIC $KSEGM, R8 /* entry to physical */
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ORR $PHYSDRAM, R8
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BL (R8)
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B dowfi
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#define ICACHELINESZ 32
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#include "cache.v7.s"
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