cinap_lenrek 12ecb3e568 usbehci: fix portreset. ... Port Reset R/W. 1=Port is in Reset. 0=Port is not in Reset. Default = 0. When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed.		2013-08-27 19:01:41 +02:00
..
doc	/sys/doc: permissions for cleanps, mkdirlist, mkfilelist	2012-10-20 19:09:54 +02:00
games/lib	fortunes: seems that so much is up on the net, it is hard to comprehend it all.	2013-08-22 12:15:29 -04:00
include	rio: add ^B control sequence to move cursor to output point	2013-08-04 06:45:58 +02:00
lib	create /sys/lib/ssl	2013-08-11 18:23:22 +02:00
man	2c(1), torrent(1), uhtml(1), kbd(3), cwfs(4), hgfs(4), cifsd(8), cryptsetup(8), hjfs(8), kbdfs(8), realemu(8), wpa(8): fix spelling, typos	2013-08-23 15:48:52 -04:00
src	usbehci: fix portreset.	2013-08-27 19:01:41 +02:00