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intel ethernet: default to 16 byte cache line size when not properly initialized and disable checksum offload for igbe (from sources)

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This commit is contained in:
cinap_lenrek 2013-04-03 21:51:42 +02:00
parent 81b394f30a
commit 6bef56f037
2 changed files with 21 additions and 25 deletions
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17
sys/src/9/pc/ether82543gc.c
View file

@ -1278,16 +1278,13 @@ gc82543pci(void)
}
cls = pcicfgr8(p, PciCLS);
switch(cls){
case 0x00:
case 0xFF:
print("82543gc: unusable cache line size\n");
free(ctlr);
continue;
case 0x08:
break;
default:
print("82543gc: cache line size %d, expected 32\n",
cls*4);
case 0x08:
case 0x10:
break;
default:
print("82543gc: p->cls %#ux, setting to 0x10\n", p->cls);
p->cls = 0x10;
pcicfgw8(p, PciCLS, p->cls);
}
ctlr->port = p->mem[0].bar & ~0x0F;
ctlr->pcidev = p;

29
sys/src/9/pc/etherigbe.c
View file

@ -1099,9 +1099,9 @@ igberxinit(Ctlr* ctlr)
csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
/*
* Enable checksum offload.
* Disable checksum offload as it has known bugs.
*/
csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
}
static int
@ -1469,8 +1469,10 @@ igbemii(Ctlr* ctlr)
* so bail.
*/
r = csr32r(ctlr, Ctrlext);
if(!(r & Mdro))
if(!(r & Mdro)) {
print("igbe: 82543gc Mdro not set\n");
return -1;
}
csr32w(ctlr, Ctrlext, r);
delay(20);
r = csr32r(ctlr, Ctrlext);
@ -1953,18 +1955,15 @@ igbepci(void)
}
cls = pcicfgr8(p, PciCLS);
switch(cls){
default:
print("igbe: unexpected CLS - %d\n", cls*4);
break;
case 0x00:
case 0xFF:
cls = 0x08;
pcicfgw8(p, PciCLS, cls);
break;
case 0x08:
case 0x10:
break;
}
default:
print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
p->cls = 0x10;
pcicfgw8(p, PciCLS, p->cls);
break;
case 0x08:
case 0x10:
break;
}
ctlr = malloc(sizeof(Ctlr));
if(ctlr == nil){
print("igbe: can't allocate memory\n");