From 6bef56f0376ea1459271bb1e23c48e358d0ae4d7 Mon Sep 17 00:00:00 2001
From: cinap_lenrek <cinap_lenrek@gmx.de>
Date: Wed, 3 Apr 2013 21:51:42 +0200
Subject: [PATCH] intel ethernet: default to 16 byte cache line size when not
 properly initialized and disable checksum offload for igbe (from sources)

---
 sys/src/9/pc/ether82543gc.c | 17 +++++++----------
 sys/src/9/pc/etherigbe.c    | 29 ++++++++++++++---------------
 2 files changed, 21 insertions(+), 25 deletions(-)

diff --git a/sys/src/9/pc/ether82543gc.c b/sys/src/9/pc/ether82543gc.c
index 8c6b56610..e90b84845 100644
--- a/sys/src/9/pc/ether82543gc.c
+++ b/sys/src/9/pc/ether82543gc.c
@@ -1278,16 +1278,13 @@ gc82543pci(void)
 		}
 		cls = pcicfgr8(p, PciCLS);
 		switch(cls){
-			case 0x00:
-			case 0xFF:
-				print("82543gc: unusable cache line size\n");
-				free(ctlr);
-				continue;
-			case 0x08:
-				break;
-			default:
-				print("82543gc: cache line size %d, expected 32\n",
-					cls*4);
+		case 0x08:
+		case 0x10:
+			break;
+		default:
+			print("82543gc: p->cls %#ux, setting to 0x10\n", p->cls);
+			p->cls = 0x10;
+			pcicfgw8(p, PciCLS, p->cls);
 		}
 		ctlr->port = p->mem[0].bar & ~0x0F;
 		ctlr->pcidev = p;
diff --git a/sys/src/9/pc/etherigbe.c b/sys/src/9/pc/etherigbe.c
index b5edff8f6..8375e9663 100644
--- a/sys/src/9/pc/etherigbe.c
+++ b/sys/src/9/pc/etherigbe.c
@@ -1099,9 +1099,9 @@ igberxinit(Ctlr* ctlr)
 	csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
 
 	/*
-	 * Enable checksum offload.
+	 * Disable checksum offload as it has known bugs.
 	 */
-	csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
+	csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
 }
 
 static int
@@ -1469,8 +1469,10 @@ igbemii(Ctlr* ctlr)
 		 * so bail.
 		 */
 		r = csr32r(ctlr, Ctrlext);
-		if(!(r & Mdro))
+		if(!(r & Mdro)) {
+			print("igbe: 82543gc Mdro not set\n");
 			return -1;
+		}
 		csr32w(ctlr, Ctrlext, r);
 		delay(20);
 		r = csr32r(ctlr, Ctrlext);
@@ -1953,18 +1955,15 @@ igbepci(void)
 		}
 		cls = pcicfgr8(p, PciCLS);
 		switch(cls){
-			default:
-				print("igbe: unexpected CLS - %d\n", cls*4);
-				break;
-			case 0x00:
-			case 0xFF:
-				cls = 0x08;
-				pcicfgw8(p, PciCLS, cls);
-				break;
-			case 0x08:
-			case 0x10:
-				break;
-		}
+		default:
+			print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
+			p->cls = 0x10;
+			pcicfgw8(p, PciCLS, p->cls);
+			break;
+		case 0x08:
+		case 0x10:
+			break;
+ 		}
 		ctlr = malloc(sizeof(Ctlr));
 		if(ctlr == nil){
 			print("igbe: can't allocate memory\n");