intel ethernet: default to 16 byte cache line size when not properly initialized and disable checksum offload for igbe (from sources)
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@ -1278,16 +1278,13 @@ gc82543pci(void)
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}
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}
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cls = pcicfgr8(p, PciCLS);
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cls = pcicfgr8(p, PciCLS);
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switch(cls){
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switch(cls){
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case 0x00:
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case 0xFF:
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print("82543gc: unusable cache line size\n");
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free(ctlr);
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continue;
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case 0x08:
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case 0x08:
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case 0x10:
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break;
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break;
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default:
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default:
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print("82543gc: cache line size %d, expected 32\n",
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print("82543gc: p->cls %#ux, setting to 0x10\n", p->cls);
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cls*4);
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p->cls = 0x10;
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pcicfgw8(p, PciCLS, p->cls);
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}
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}
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ctlr->port = p->mem[0].bar & ~0x0F;
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ctlr->port = p->mem[0].bar & ~0x0F;
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ctlr->pcidev = p;
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ctlr->pcidev = p;
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@ -1099,9 +1099,9 @@ igberxinit(Ctlr* ctlr)
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csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
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csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
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/*
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/*
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* Enable checksum offload.
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* Disable checksum offload as it has known bugs.
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*/
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*/
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csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
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csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
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}
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}
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static int
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static int
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@ -1469,8 +1469,10 @@ igbemii(Ctlr* ctlr)
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* so bail.
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* so bail.
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*/
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*/
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r = csr32r(ctlr, Ctrlext);
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r = csr32r(ctlr, Ctrlext);
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if(!(r & Mdro))
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if(!(r & Mdro)) {
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print("igbe: 82543gc Mdro not set\n");
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return -1;
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return -1;
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}
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csr32w(ctlr, Ctrlext, r);
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csr32w(ctlr, Ctrlext, r);
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delay(20);
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delay(20);
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r = csr32r(ctlr, Ctrlext);
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r = csr32r(ctlr, Ctrlext);
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@ -1954,12 +1956,9 @@ igbepci(void)
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cls = pcicfgr8(p, PciCLS);
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cls = pcicfgr8(p, PciCLS);
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switch(cls){
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switch(cls){
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default:
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default:
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print("igbe: unexpected CLS - %d\n", cls*4);
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print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
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break;
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p->cls = 0x10;
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case 0x00:
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pcicfgw8(p, PciCLS, p->cls);
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case 0xFF:
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cls = 0x08;
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pcicfgw8(p, PciCLS, cls);
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break;
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break;
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case 0x08:
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case 0x08:
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case 0x10:
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case 0x10:
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