bcm64: add gic interrupt controller driver for raspberry pi 4
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cinap_lenrek
parent
10b456ff44
commit
676ef0ca0b
2 changed files with 305 additions and 0 deletions
295
sys/src/9/bcm64/gic.c
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295
sys/src/9/bcm64/gic.c
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "sysreg.h"
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#include "../port/error.h"
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enum {
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GICD_CTLR = 0x000/4, /* RW, Distributor Control Register */
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GICD_TYPER = 0x004/4, /* RO, Interrupt Controller Type */
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GICD_IIDR = 0x008/4, /* RO, Distributor Implementer Identification Register */
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GICD_IGROUPR0 = 0x080/4, /* RW, Interrupt Group Registers (0x80-0xBC) */
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GICD_ISENABLER0 = 0x100/4, /* RW, Interrupt Set-Enable Registers (0x100-0x13C) */
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GICD_ICENABLER0 = 0x180/4, /* RW, Interrupt Clear-Enable Registers (0x180-0x1BC) */
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GICD_ISPENDR0 = 0x200/4, /* RW, Interrupt Set-Pending Registers (0x200-0x23C) */
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GICD_ICPENDR0 = 0x280/4, /* RW, Interrupt Clear-Pending Registers (0x280-0x2BC) */
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GICD_ISACTIVER0 = 0x300/4, /* RW, Interrupt Set-Active Registers (0x300-0x33C) */
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GICD_ICACTIVER0 = 0x380/4, /* RW, Interrupt Clear-Active Registers (0x380-0x3BC) */
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GICD_IPRIORITYR0= 0x400/4, /* RW, Interrupt Priority Registers (0x400-0x5FC) */
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GICD_TARGETSR0 = 0x800/4, /* RW, Interrupt Target Registers (0x800-0x9FC) */
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GICD_ICFGR0 = 0xC00/4, /* RW, Interrupt Configuration Registers (0xC00-0xC7C) */
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GICD_ISR0 = 0xD00/4,
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GICD_PPISR = GICD_ISR0, /* RO, Private Peripheral Interrupt Status Register */
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GICD_SPISR0 = GICD_ISR0+1, /* RO, Shared Peripheral Interrupt Status Register */
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GICD_SGIR = 0xF00/4, /* WO, Software Generated Interrupt Register */
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GICD_CPENDSGIR0 = 0xF10/4, /* RW, SGI Clear-Pending Registers (0xF10-0xF1C) */
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GICD_SPENDSGIR0 = 0xF20/4, /* RW, SGI Set-Pending Registers (0xF20-0xF2C) */
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GICD_PIDR4 = 0xFD0/4, /* RO, Perpheral ID Registers */
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GICD_PIDR5 = 0xFD4/4,
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GICD_PIDR6 = 0xFD8/4,
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GICD_PIDR7 = 0xFDC/4,
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GICD_PIDR0 = 0xFE0/4,
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GICD_PIDR1 = 0xFE4/4,
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GICD_PIDR2 = 0xFE8/4,
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GICD_PIDR3 = 0xFEC/4,
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GICD_CIDR0 = 0xFF0/4, /* RO, Component ID Registers */
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GICD_CIDR1 = 0xFF4/4,
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GICD_CIDR2 = 0xFF8/4,
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GICD_CIDR3 = 0xFFC/4,
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GICC_CTLR = 0x000/4, /* RW, CPU Interace Control Register */
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GICC_PMR = 0x004/4, /* RW, Interrupt Priority Mask Register */
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GICC_BPR = 0x008/4, /* RW, Binary Point Register */
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GICC_IAR = 0x00C/4, /* RO, Interrupt Acknowledge Register */
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GICC_EOIR = 0x010/4, /* WO, End of Interrupt Register */
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GICC_RPR = 0x014/4, /* RO, Running Priority Register */
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GICC_HPPIR = 0x018/4, /* RO, Highest Priority Pending Interrupt Register */
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GICC_ABPR = 0x01C/4, /* RW, Aliased Binary Point Register */
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GICC_AIAR = 0x020/4, /* RO, Aliased Interrupt Acknowledge Register */
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GICC_AEOIR = 0x024/4, /* WO, Aliased End of Interrupt Register */
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GICC_AHPPIR = 0x028/4, /* RO, Aliased Highest Priority Pending Interrupt Register */
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GICC_APR0 = 0x0D0/4, /* RW, Active Priority Register */
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GICC_NSAPR0 = 0x0E0/4, /* RW, Non-Secure Active Priority Register */
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GICC_IIDR = 0x0FC/4, /* RO, CPU Interface Identification Register */
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GICC_DIR = 0x1000/4, /* WO, Deactivate Interrupt Register */
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GICH_HCR = 0x000/4, /* RW, Hypervisor Control Register */
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GICH_VTR = 0x004/4, /* RO, VGIC Type Register */
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GICH_VMCR = 0x008/4, /* RW, Virtual Machine Control Register */
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GICH_MISR = 0x010/4, /* RO, Maintenance Interrupt Status Register */
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GICH_EISR0 = 0x020/4, /* RO, End of Interrupt Status Register */
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GICH_ELSR0 = 0x030/4, /* RO, Empty List Register Status Register */
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GICH_APR0 = 0x0F0/4, /* RW, Active Priority Register */
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GICH_LR0 = 0x100/4, /* RW, List Registers (0x100-0x10C) */
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GICV_CTLR = 0x000/4, /* RW, Virtual Machine Control Register */
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GICV_PMR = 0x004/4, /* RW, VM Priority Mask Register */
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GICV_BPR = 0x008/4, /* RW, VM Binary Point Register */
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GICV_IAR = 0x00C/4, /* RO, VM Interrupt Acknowledge Register */
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GICV_EOIR = 0x010/4, /* WO, VM End of Interrupt Register */
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GICV_RPR = 0x014/4, /* RO, VM Running Priority Register */
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GICV_HPPIR = 0x018/4, /* RO, VM Highest Piority Pending Interrupt Register */
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GICV_ABPR = 0x01C/4, /* RW, VM Aliased Binary Point Register */
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GICV_AIAR = 0x020/4, /* RO, VM Aliased Interrupt Acknowledge Register */
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GICV_AEOIR = 0x024/4, /* WO, VM Aliased End of Interrupt Register */
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GICV_AHPPIR = 0x028/4, /* RO, VM Aliaed Highest Piority Pending Interrupt Register */
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GICV_APR0 = 0x0D0/4, /* RW, VM Active Priority Register */
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GICV_IIDR = 0x0FC/4, /* RO, VM CPU Interface Identification Register */
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GICV_DIR = 0x1000/4, /* WO, VM Deactivate Interrupt Register */
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};
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typedef struct Vctl Vctl;
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struct Vctl {
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Vctl *next;
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void (*f)(Ureg*, void*);
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void *a;
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int irq;
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u32int intid;
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};
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static Lock vctllock;
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static Vctl *vctl[MAXMACH][32], *vfiq;
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static u32int *cregs, *dregs;
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void
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intrcpushutdown(void)
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{
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if(cregs == nil || dregs == nil){
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uintptr va, pa;
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pa = sysrd(CBAR_EL1);
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va = ARMLOCAL + (pa - soc.armlocal);
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dregs = (u32int*)(va + 0x1000);
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cregs = (u32int*)(va + 0x2000);
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}
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/* disable cpu interface */
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cregs[GICC_CTLR] &= ~1;
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coherence();
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}
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void
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intrsoff(void)
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{
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int i, n;
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intrcpushutdown();
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/* disable distributor */
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dregs[GICD_CTLR] &= ~1;
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coherence();
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/* clear all interrupts */
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n = ((dregs[GICD_TYPER] & 0x1F)+1) << 5;
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for(i = 0; i < n; i += 32){
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dregs[GICD_ISENABLER0 + (i/32)] = -1;
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coherence();
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dregs[GICD_ICENABLER0 + (i/32)] = -1;
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coherence();
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}
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for(i = 0; i < n; i += 4){
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dregs[GICD_IPRIORITYR0 + (i/4)] = 0;
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dregs[GICD_TARGETSR0 + (i/4)] = 0;
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}
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for(i = 32; i < n; i += 16)
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dregs[GICD_ICFGR0 + (i/16)] = 0;
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coherence();
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}
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/*
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* called by trap to handle irq interrupts.
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* returns true iff a clock interrupt, thus maybe reschedule.
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*/
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int
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irq(Ureg* ureg)
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{
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Vctl *v;
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int clockintr;
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u32int intid;
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m->intr++;
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intid = cregs[GICC_IAR] & 0xFFFFFF;
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if((intid & ~3) == 1020)
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return 0; // spurious
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clockintr = 0;
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for(v = vctl[m->machno][intid%32]; v != nil; v = v->next)
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if(v->intid == intid){
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coherence();
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v->f(ureg, v->a);
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coherence();
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if(v->irq == IRQclock || v->irq == IRQcntps || v->irq == IRQcntpns)
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clockintr = 1;
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}
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coherence();
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cregs[GICC_EOIR] = intid;
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return clockintr;
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}
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/*
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* called direct from lexception.s to handle fiq interrupt.
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*/
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void
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fiq(Ureg *ureg)
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{
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Vctl *v;
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u32int intid;
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m->intr++;
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intid = cregs[GICC_IAR] & 0xFFFFFF;
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if((intid & ~3) == 1020)
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return; // spurious
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v = vfiq;
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if(v != nil && v->intid == intid && m->machno == 0){
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coherence();
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v->f(ureg, v->a);
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coherence();
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}
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cregs[GICC_EOIR] = intid;
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}
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void
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intrenable(int irq, void (*f)(Ureg*, void*), void *a, int tbdf, char*)
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{
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Vctl *v;
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u32int intid;
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int cpu, prio;
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if(BUSTYPE(tbdf) == BusPCI){
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pciintrenable(tbdf, f, a);
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return;
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}
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if(tbdf != BUSUNKNOWN)
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return;
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cpu = 0;
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prio = 0x80;
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intid = irq;
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switch(irq){
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case IRQcntps:
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intid = 16 + 13;
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break;
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case IRQcntpns:
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intid = 16 + 14;
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break;
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case IRQmbox0:
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case IRQmbox1:
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case IRQmbox2:
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case IRQmbox3:
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case IRQlocaltmr:
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print("irqenable: missing documentation for local irq %d\n", irq);
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return;
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default:
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if(irq < IRQgic){
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if(irq < 64)
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intid += IRQgic-64;
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else if(irq >= IRQbasic)
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intid += IRQgic-64-32-8-IRQbasic;
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}
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}
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if(intid < 32)
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cpu = m->machno;
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if((v = xalloc(sizeof(Vctl))) == nil)
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panic("irqenable: no mem");
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v->irq = irq;
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v->intid = intid;
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v->f = f;
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v->a = a;
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lock(&vctllock);
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if(irq == IRQfiq){
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vfiq = v;
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prio = 0;
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}else{
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v->next = vctl[cpu][intid%32];
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vctl[cpu][intid%32] = v;
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}
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/* enable cpu interface */
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cregs[GICC_PMR] = 0xFF;
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coherence();
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cregs[GICC_CTLR] |= 1;
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coherence();
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cregs[GICC_EOIR] = intid;
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/* enable distributor */
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dregs[GICD_CTLR] |= 1;
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coherence();
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/* setup */
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dregs[GICD_IPRIORITYR0 + (intid/4)] |= prio << ((intid%4) << 3);
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dregs[GICD_TARGETSR0 + (intid/4)] |= (1<<cpu) << ((intid%4) << 3);
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coherence();
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/* turn on */
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dregs[GICD_ISENABLER0 + (intid/32)] = 1 << (intid%32);
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coherence();
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unlock(&vctllock);
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}
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void
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intrdisable(int, void (*f)(Ureg*, void*), void *a, int tbdf, char*)
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{
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if(BUSTYPE(tbdf) == BusPCI){
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pciintrdisable(tbdf, f, a);
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return;
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}
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}
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@ -1,6 +1,15 @@
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#define MIDR_EL1 SYSREG(3,0,0,0,0)
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#define MPIDR_EL1 SYSREG(3,0,0,0,5)
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#define ID_AA64AFR0_EL1 SYSREG(3,0,0,5,4)
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#define ID_AA64AFR1_EL1 SYSREG(3,0,0,5,5)
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#define ID_AA64DFR0_EL1 SYSREG(3,0,0,5,0)
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#define ID_AA64DFR1_EL1 SYSREG(3,0,0,5,1)
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#define ID_AA64ISAR0_EL1 SYSREG(3,0,0,6,0)
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#define ID_AA64ISAR1_EL1 SYSREG(3,0,0,6,1)
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#define ID_AA64MMFR0_EL1 SYSREG(3,0,0,7,0)
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#define ID_AA64MMFR1_EL1 SYSREG(3,0,0,7,1)
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#define ID_AA64PFR0_EL1 SYSREG(3,0,0,4,0)
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#define ID_AA64PFR1_EL1 SYSREG(3,0,0,4,1)
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#define SCTLR_EL1 SYSREG(3,0,1,0,0)
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#define CPACR_EL1 SYSREG(3,0,1,0,2)
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#define MAIR_EL1 SYSREG(3,0,10,2,0)
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@ -35,6 +44,7 @@
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#define ACTLR_EL2 SYSREG(3,4,1,0,1)
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#define CPUACTLR_EL1 SYSREG(3,1,15,2,0)
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#define CPUECTLR_EL1 SYSREG(3,1,15,2,1)
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#define CBAR_EL1 SYSREG(3,1,15,3,0)
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/* l.s redefines this for the assembler */
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#define SYSREG(op0,op1,Cn,Cm,op2) ((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5)
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