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bcm64: add gisb arbiter driver to catch bus timeouts

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This commit is contained in:
cinap_lenrek 2019-07-25 09:01:44 +02:00
parent 811b80cae1
commit 10b456ff44
2 changed files with 67 additions and 0 deletions
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63
sys/src/9/bcm64/gisb.c Normal file
View file

@ -0,0 +1,63 @@
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "../port/error.h"
#include "ureg.h"
/*
* GISB arbiter registers
*/
static u32int *regs = (u32int*)(VIRTIO2 + 0x400000);
enum {
ArbTimer = 0x008/4,
ArbErrCapClear = 0x7e4/4,
ArbErrCapAddrHi = 0x7e8/4,
ArbErrCapAddr = 0x7ec/4,
ArbErrCapStatus = 0x7f4/4,
CapStatusTimeout = 1<<12,
CapStatusAbort = 1<<11,
CapStatusWrite = 1<<1,
CapStatusValid = 1<<0,
ArbErrCapMaster = 0x7f8/4,
};
static int
arbinterrupt(Ureg *)
{
u32int status = regs[ArbErrCapStatus];
u32int master;
uvlong addr;
if((status & CapStatusValid) == 0)
return 0;
master = regs[ArbErrCapMaster];
addr = regs[ArbErrCapAddr];
addr |= (uvlong)regs[ArbErrCapAddrHi]<<32;
regs[ArbErrCapClear] = CapStatusValid;
iprint("cpu%d: GISB arbiter error: %s%s %s bus addr %llux, master %.8ux\n",
m->machno,
(status & CapStatusTimeout) ? "timeout" : "",
(status & CapStatusAbort) ? "abort" : "",
(status & CapStatusWrite) ? "writing" : "reading",
addr,
master);
return 1;
}
void
gisblink(void)
{
extern int (*buserror)(Ureg*); // trap.c
regs[ArbErrCapClear] = CapStatusValid;
buserror = arbinterrupt;
}

4
sys/src/9/bcm64/trap.c
View file

@ -10,6 +10,8 @@
#include "ureg.h"
#include "sysreg.h"
int (*buserror)(Ureg*);
/* SPSR bits user can modify */
#define USPSRMASK (0xFULL<<28)
@ -141,6 +143,8 @@ trap(Ureg *ureg)
}
if(intr == 3){
case 0x2F: // SError interrupt
if(buserror != nil && (*buserror)(ureg))
break;
dumpregs(ureg);
panic("SError interrupt");
break;