2022-06-14 23:53:03 +00:00
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/sd.h"
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enum {
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Initfreq = 400000, /* initialisation frequency for MMC */
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SDfreq = 25*Mhz, /* standard SD frequency */
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DTO = 14, /* data timeout exponent (guesswork) */
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GoIdle = 0, /* mmc/sdio go idle state */
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MMCSelect = 7, /* mmc/sd card select command */
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Setbuswidth = 6, /* mmc/sd set bus width command */
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Switchfunc = 6, /* mmc/sd switch function command */
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2022-06-18 12:45:39 +00:00
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Voltageswitch = 11, /* md/sdio switch to 1.8V */
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IORWdirect = 52, /* sdio read/write direct command */
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IORWextended = 53, /* sdio read/write extended command */
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Appcmd = 55, /* mmc/sd application command prefix */
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2022-06-14 23:53:03 +00:00
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};
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enum {
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/* Controller registers */
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SDMAaddr = 0x00>>2,
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Blksizecnt = 0x04>>2,
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Arg1 = 0x08>>2,
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Cmdtm = 0x0c>>2,
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Resp0 = 0x10>>2,
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Resp1 = 0x14>>2,
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Resp2 = 0x18>>2,
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Resp3 = 0x1c>>2,
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Data = 0x20>>2,
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Status = 0x24>>2,
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Control0 = 0x28>>2,
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Control1 = 0x2c>>2,
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Interrupt = 0x30>>2,
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Irptmask = 0x34>>2,
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Irpten = 0x38>>2,
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Control2 = 0x3c>>2,
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Capability = 0x40>>2,
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Mixctrl = 0x48>>2,
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Forceirpt = 0x50>>2,
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Dmadesc = 0x58>>2,
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Vendorspec = 0xC0>>2,
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/* Vendorspec */
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ClkEn = 1<<14,
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PerEn = 1<<13,
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HclkEn = 1<<12,
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IpgEn = 1<<11,
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Vsel = 1<<1,
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/* Control0 (PROT_CTRL) */
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Dmaselect = 3<<8,
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DmaSDMA = 0<<8,
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DmaADMA1 = 1<<8,
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DmaADMA2 = 2<<8,
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EMODE = 3<<4,
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2022-06-14 23:53:03 +00:00
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BE = 0<<4,
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HBE = 1<<4,
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LE = 2<<4,
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DwidthMask = 3<<1,
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Dwidth8 = 2<<1,
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Dwidth4 = 1<<1,
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Dwidth1 = 0<<1,
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LED = 1<<0,
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/* Control1 (SYS_CTRL) */
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Srstdata = 1<<26, /* reset data circuit */
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Srstcmd = 1<<25, /* reset command circuit */
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Srsthc = 1<<24, /* reset complete host controller */
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Datatoshift = 16, /* data timeout unit exponent */
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Datatomask = 0xF0000,
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SDCLKFSshift = 8,
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DVSshift = 4,
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/* Cmdtm */
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Indexshift = 24,
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Suspend = 1<<22,
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Resume = 2<<22,
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Abort = 3<<22,
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Isdata = 1<<21,
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Ixchken = 1<<20,
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Crcchken = 1<<19,
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Respmask = 3<<16,
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Respnone = 0<<16,
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Resp136 = 1<<16,
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Resp48 = 2<<16,
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Resp48busy = 3<<16,
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/* Mixctrl */
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Autocmd23 = 1<<7,
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Multiblock = 1<<5,
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Host2card = 0<<4,
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Card2host = 1<<4,
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DdrEn = 1<<3,
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Autocmd12 = 1<<2,
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Blkcnten = 1<<1,
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Dmaen = 1<<0,
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MixCmdMask = 0xFF ^ DdrEn,
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/* Interrupt */
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Admaerr = 1<<28,
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Acmderr = 1<<24,
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Denderr = 1<<22,
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Dcrcerr = 1<<21,
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Dtoerr = 1<<20,
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Cbaderr = 1<<19,
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Cenderr = 1<<18,
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Ccrcerr = 1<<17,
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Ctoerr = 1<<16,
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Err = Admaerr|Acmderr|Denderr|Dcrcerr|Dtoerr|Cbaderr|Cenderr|Ccrcerr|Ctoerr,
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Cardintr = 1<<8,
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Cardinsert = 1<<6,
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Readrdy = 1<<5,
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Writerdy = 1<<4,
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Dmaintr = 1<<3,
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Datadone = 1<<1,
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Cmddone = 1<<0,
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/* Status */
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Bufread = 1<<11,
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Bufwrite = 1<<10,
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Readtrans = 1<<9,
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Writetrans = 1<<8,
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Clkstable = 1<<3,
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Datactive = 1<<2,
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Datinhibit = 1<<1,
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Cmdinhibit = 1<<0,
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};
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static int cmdinfo[64] = {
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[0] Ixchken,
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[2] Resp136,
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[3] Resp48 | Ixchken | Crcchken,
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[5] Resp48,
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[6] Resp48 | Ixchken | Crcchken,
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[7] Resp48 | Ixchken | Crcchken,
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[8] Resp48 | Ixchken | Crcchken,
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[9] Resp136,
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[11] Resp48 | Ixchken | Crcchken,
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[13] Resp48 | Ixchken | Crcchken,
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[16] Resp48,
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[17] Resp48 | Isdata | Card2host | Ixchken | Crcchken,
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[18] Resp48 | Isdata | Card2host | Multiblock | Blkcnten | Ixchken | Crcchken | Autocmd12,
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[24] Resp48 | Isdata | Host2card | Ixchken | Crcchken,
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[25] Resp48 | Isdata | Host2card | Multiblock | Blkcnten | Ixchken | Crcchken | Autocmd12,
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[41] Resp48,
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[52] Resp48 | Ixchken | Crcchken,
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[53] Resp48 | Ixchken | Crcchken | Isdata,
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[55] Resp48 | Ixchken | Crcchken,
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};
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typedef struct Adma Adma;
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typedef struct Ctlr Ctlr;
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/*
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* ADMA2 descriptor
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* See SD Host Controller Simplified Specification Version 2.00
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*/
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struct Adma {
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u32int desc;
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u32int addr;
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};
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enum {
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/* desc fields */
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Valid = 1<<0,
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End = 1<<1,
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Int = 1<<2,
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Nop = 0<<4,
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Tran = 2<<4,
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Link = 3<<4,
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OLength = 16,
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/* maximum value for Length field */
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Maxdma = 1<<12,
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};
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struct Ctlr {
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Rendez r;
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int fastclock;
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uint extclk;
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int appcmd;
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Adma *dma;
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};
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2022-06-18 12:45:39 +00:00
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static Ctlr usdhc;
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2022-06-14 23:53:03 +00:00
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2022-06-18 12:45:39 +00:00
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static void usdhcinterrupt(Ureg*, void*);
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static u32int *regs = (u32int*)(VIRTIO+0xB50000); /* USDHC2 */
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#define RR(reg) (regs[reg])
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2022-06-14 23:53:03 +00:00
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static void
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WR(int reg, u32int val)
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{
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if(0)print("WR %2.2ux %ux\n", reg<<2, val);
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coherence();
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regs[reg] = val;
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}
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static Adma*
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dmaalloc(void *addr, int len)
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{
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int n;
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uintptr a;
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Adma *adma, *p;
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a = (uintptr)addr;
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n = (len + Maxdma-1) / Maxdma;
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adma = sdmalloc(n * sizeof(Adma));
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for(p = adma; len > 0; p++){
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p->desc = Valid | Tran;
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if(n == 1)
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p->desc |= len<<OLength | End | Int;
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else
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p->desc |= Maxdma<<OLength;
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p->addr = PADDR(a);
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a += Maxdma;
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len -= Maxdma;
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n--;
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}
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cachedwbse(adma, (char*)p - (char*)adma);
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return adma;
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}
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static void
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2022-06-18 12:45:39 +00:00
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usdhcclk(uint freq)
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{
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uint pre_div = 1, post_div = 1, clk = usdhc.extclk;
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2022-06-14 23:53:03 +00:00
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while(clk / (pre_div * 16) > freq && pre_div < 256)
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pre_div <<= 1;
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while(clk / (pre_div * post_div) > freq && post_div < 16)
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post_div++;
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2022-06-18 12:45:39 +00:00
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WR(Vendorspec, RR(Vendorspec) & ~ClkEn);
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2022-06-14 23:53:03 +00:00
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WR(Control1, (pre_div>>1)<<SDCLKFSshift | (post_div-1)<<DVSshift | DTO<<Datatoshift);
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delay(10);
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2022-06-18 12:45:39 +00:00
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WR(Vendorspec, RR(Vendorspec) | ClkEn | PerEn);
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while((RR(Status) & Clkstable) == 0)
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;
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}
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static int
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datadone(void*)
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{
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return RR(Interrupt) & (Datadone|Err);
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}
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static int
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usdhcinit(void)
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{
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iomuxpad("pad_sd2_clk", "usdhc2_clk", "~LVTTL ~HYS ~PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_cmd", "usdhc2_cmd", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data0", "usdhc2_data0", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data1", "usdhc2_data1", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data2", "usdhc2_data2", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data3", "usdhc2_data3", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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setclkgate("usdhc2.ipg_clk", 0);
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setclkgate("usdhc2.ipg_clk_perclk", 0);
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setclkrate("usdhc2.ipg_clk_perclk", "system_pll1_clk", 200*Mhz);
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setclkgate("usdhc2.ipg_clk_perclk", 1);
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2022-06-18 12:45:39 +00:00
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setclkgate("usdhc2.ipg_clk", 1);
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usdhc.extclk = getclkrate("usdhc2.ipg_clk_perclk");
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if(usdhc.extclk <= 0){
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print("usdhc: usdhc2.ipg_clk_perclk not enabled\n");
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return -1;
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}
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2022-06-18 12:45:39 +00:00
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if(0)print("usdhc control %8.8ux %8.8ux %8.8ux\n",
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RR(Control0), RR(Control1), RR(Control2));
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2022-06-14 23:53:03 +00:00
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WR(Control1, Srsthc);
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delay(10);
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while(RR(Control1) & Srsthc)
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;
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WR(Control1, Srstdata);
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delay(10);
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WR(Control1, 0);
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return 0;
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}
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static int
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usdhcinquiry(char *inquiry, int inqlen)
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2022-06-14 23:53:03 +00:00
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{
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return snprint(inquiry, inqlen, "USDHC Host Controller");
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}
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static void
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usdhcenable(void)
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{
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WR(Control0, 0);
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delay(1);
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WR(Vendorspec, RR(Vendorspec) & ~Vsel);
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2022-06-14 23:53:03 +00:00
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WR(Control0, LE | Dwidth1 | DmaADMA2);
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WR(Control1, 0);
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delay(1);
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2022-06-18 12:45:39 +00:00
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WR(Vendorspec, RR(Vendorspec) | HclkEn | IpgEn);
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usdhcclk(Initfreq);
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WR(Irpten, 0);
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WR(Irptmask, ~(Cardintr|Dmaintr));
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WR(Interrupt, ~0);
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2022-06-18 12:45:39 +00:00
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intrenable(IRQusdhc2, usdhcinterrupt, nil, BUSUNKNOWN, "usdhc2");
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}
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static int
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usdhccmd(u32int cmd, u32int arg, u32int *resp)
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2022-06-14 23:53:03 +00:00
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{
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u32int c;
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int i;
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ulong now;
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/* using Autocmd12 */
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if(cmd == 12)
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return 0;
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assert(cmd < nelem(cmdinfo) && cmdinfo[cmd] != 0);
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c = (cmd << Indexshift) | cmdinfo[cmd];
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/*
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* CMD6 may be Setbuswidth or Switchfunc depending on Appcmd prefix
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*/
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2022-06-18 12:45:39 +00:00
|
|
|
if(cmd == Switchfunc && !usdhc.appcmd)
|
2022-06-14 23:53:03 +00:00
|
|
|
c |= Isdata|Card2host;
|
|
|
|
if(c & Isdata)
|
|
|
|
c |= Dmaen;
|
|
|
|
if(cmd == IORWextended){
|
|
|
|
if(arg & (1<<31))
|
|
|
|
c |= Host2card;
|
|
|
|
else
|
|
|
|
c |= Card2host;
|
2022-06-18 12:45:39 +00:00
|
|
|
if((RR(Blksizecnt)&0xFFFF0000) != 0x10000)
|
2022-06-14 23:53:03 +00:00
|
|
|
c |= Multiblock | Blkcnten;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* GoIdle indicates new card insertion: reset bus width & speed
|
|
|
|
*/
|
|
|
|
if(cmd == GoIdle){
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
|
|
|
|
usdhcclk(Initfreq);
|
2022-06-14 23:53:03 +00:00
|
|
|
}
|
2022-06-18 12:45:39 +00:00
|
|
|
if(RR(Status) & Cmdinhibit){
|
|
|
|
print("usdhccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
|
|
|
|
RR(Interrupt), RR(Status));
|
|
|
|
WR(Control1, RR(Control1) | Srstcmd);
|
|
|
|
while(RR(Control1) & Srstcmd)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
2022-06-18 12:45:39 +00:00
|
|
|
while(RR(Status) & Cmdinhibit)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
|
|
|
}
|
2022-06-18 12:45:39 +00:00
|
|
|
if((RR(Status) & Datinhibit) &&
|
2022-06-14 23:53:03 +00:00
|
|
|
((c & Isdata) || (c & Respmask) == Resp48busy)){
|
2022-06-18 12:45:39 +00:00
|
|
|
print("usdhccmd: need to reset Datinhibit intr %ux stat %ux\n",
|
|
|
|
RR(Interrupt), RR(Status));
|
|
|
|
WR(Control1, RR(Control1) | Srstdata);
|
|
|
|
while(RR(Control1) & Srstdata)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
2022-06-18 12:45:39 +00:00
|
|
|
while(RR(Status) & Datinhibit)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
|
|
|
}
|
2022-06-18 12:45:39 +00:00
|
|
|
while(RR(Status) & Datactive)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
|
|
|
WR(Arg1, arg);
|
2022-06-18 12:45:39 +00:00
|
|
|
if((i = (RR(Interrupt) & ~Cardintr)) != 0){
|
2022-06-14 23:53:03 +00:00
|
|
|
if(i != Cardinsert)
|
2022-06-18 12:45:39 +00:00
|
|
|
print("usdhc: before command, intr was %ux\n", i);
|
2022-06-14 23:53:03 +00:00
|
|
|
WR(Interrupt, i);
|
|
|
|
}
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Mixctrl, (RR(Mixctrl) & ~MixCmdMask) | (c & MixCmdMask));
|
2022-06-14 23:53:03 +00:00
|
|
|
WR(Cmdtm, c & ~0xFFFF);
|
|
|
|
|
|
|
|
now = MACHP(0)->ticks;
|
2022-06-18 12:45:39 +00:00
|
|
|
while(((i=RR(Interrupt))&(Cmddone|Err)) == 0)
|
2022-06-14 23:53:03 +00:00
|
|
|
if(MACHP(0)->ticks - now > HZ)
|
|
|
|
break;
|
|
|
|
if((i&(Cmddone|Err)) != Cmddone){
|
|
|
|
if((i&~(Err|Cardintr)) != Ctoerr)
|
2022-06-18 12:45:39 +00:00
|
|
|
print("usdhc: cmd %ux arg %ux error intr %ux stat %ux\n", c, arg, i, RR(Status));
|
2022-06-14 23:53:03 +00:00
|
|
|
WR(Interrupt, i);
|
2022-06-18 12:45:39 +00:00
|
|
|
if(RR(Status)&Cmdinhibit){
|
|
|
|
WR(Control1, RR(Control1)|Srstcmd);
|
|
|
|
while(RR(Control1)&Srstcmd)
|
2022-06-14 23:53:03 +00:00
|
|
|
;
|
|
|
|
}
|
|
|
|
error(Eio);
|
|
|
|
}
|
|
|
|
WR(Interrupt, i & ~(Datadone|Readrdy|Writerdy));
|
|
|
|
switch(c & Respmask){
|
|
|
|
case Resp136:
|
2022-06-18 12:45:39 +00:00
|
|
|
resp[0] = RR(Resp0)<<8;
|
|
|
|
resp[1] = RR(Resp0)>>24 | RR(Resp1)<<8;
|
|
|
|
resp[2] = RR(Resp1)>>24 | RR(Resp2)<<8;
|
|
|
|
resp[3] = RR(Resp2)>>24 | RR(Resp3)<<8;
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
case Resp48:
|
|
|
|
case Resp48busy:
|
2022-06-18 12:45:39 +00:00
|
|
|
resp[0] = RR(Resp0);
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
case Respnone:
|
|
|
|
resp[0] = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if((c & Respmask) == Resp48busy){
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Irpten, RR(Irpten)|Datadone|Err);
|
|
|
|
tsleep(&usdhc.r, datadone, 0, 1000);
|
|
|
|
i = RR(Interrupt);
|
2022-06-14 23:53:03 +00:00
|
|
|
if((i & Datadone) == 0)
|
2022-06-18 12:45:39 +00:00
|
|
|
print("usdhcio: no Datadone in %x after CMD%d\n", i, cmd);
|
2022-06-14 23:53:03 +00:00
|
|
|
if(i & Err)
|
2022-06-18 12:45:39 +00:00
|
|
|
print("usdhcio: CMD%d error interrupt %ux\n",
|
|
|
|
cmd, RR(Interrupt));
|
2022-06-14 23:53:03 +00:00
|
|
|
if(i != 0) WR(Interrupt, i);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Once card is selected, use faster clock
|
|
|
|
*/
|
|
|
|
if(cmd == MMCSelect){
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhcclk(SDfreq);
|
|
|
|
usdhc.fastclock = 1;
|
2022-06-14 23:53:03 +00:00
|
|
|
}
|
|
|
|
if(cmd == Setbuswidth){
|
2022-06-18 12:45:39 +00:00
|
|
|
if(usdhc.appcmd){
|
2022-06-14 23:53:03 +00:00
|
|
|
/*
|
|
|
|
* If card bus width changes, change host bus width
|
|
|
|
*/
|
|
|
|
switch(arg){
|
|
|
|
case 0:
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth4);
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}else if(cmd == IORWdirect && (arg & ~0xFF) == (1<<31|0<<28|7<<9)){
|
|
|
|
switch(arg & 0x3){
|
|
|
|
case 0:
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth4);
|
2022-06-14 23:53:03 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhc.appcmd = (cmd == Appcmd);
|
2022-06-14 23:53:03 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhciosetup(int write, void *buf, int bsize, int bcount)
|
2022-06-14 23:53:03 +00:00
|
|
|
{
|
2022-06-18 12:45:39 +00:00
|
|
|
int len = bsize * bcount;
|
2022-06-14 23:53:03 +00:00
|
|
|
assert(((uintptr)buf&3) == 0);
|
|
|
|
assert((len&3) == 0);
|
|
|
|
assert(bsize <= 2048);
|
|
|
|
WR(Blksizecnt, bcount<<16 | bsize);
|
2022-06-18 12:45:39 +00:00
|
|
|
if(usdhc.dma)
|
|
|
|
sdfree(usdhc.dma);
|
|
|
|
usdhc.dma = dmaalloc(buf, len);
|
2022-06-14 23:53:03 +00:00
|
|
|
if(write)
|
|
|
|
cachedwbse(buf, len);
|
|
|
|
else
|
|
|
|
cachedwbinvse(buf, len);
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Dmadesc, PADDR(usdhc.dma));
|
2022-06-14 23:53:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhcio(int write, uchar *buf, int len)
|
2022-06-14 23:53:03 +00:00
|
|
|
{
|
2022-06-18 12:45:39 +00:00
|
|
|
u32int i;
|
2022-06-14 23:53:03 +00:00
|
|
|
|
2022-06-18 12:45:39 +00:00
|
|
|
WR(Irpten, RR(Irpten) | Datadone|Err);
|
|
|
|
tsleep(&usdhc.r, datadone, 0, 3000);
|
|
|
|
WR(Irpten, RR(Irpten) & ~(Datadone|Err));
|
|
|
|
i = RR(Interrupt);
|
2022-06-14 23:53:03 +00:00
|
|
|
if((i & (Datadone|Err)) != Datadone){
|
|
|
|
print("sdhc: %s error intr %ux stat %ux\n",
|
2022-06-18 12:45:39 +00:00
|
|
|
write? "write" : "read", i, RR(Status));
|
2022-06-14 23:53:03 +00:00
|
|
|
WR(Interrupt, i);
|
|
|
|
error(Eio);
|
|
|
|
}
|
|
|
|
WR(Interrupt, i);
|
|
|
|
if(!write)
|
|
|
|
cachedinvse(buf, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhcinterrupt(Ureg*, void*)
|
2022-06-14 23:53:03 +00:00
|
|
|
{
|
2022-06-18 12:45:39 +00:00
|
|
|
u32int i;
|
2022-06-14 23:53:03 +00:00
|
|
|
|
2022-06-18 12:45:39 +00:00
|
|
|
i = RR(Interrupt);
|
2022-06-14 23:53:03 +00:00
|
|
|
if(i&(Datadone|Err))
|
2022-06-18 12:45:39 +00:00
|
|
|
wakeup(&usdhc.r);
|
|
|
|
WR(Irpten, RR(Irpten) & ~i);
|
2022-06-14 23:53:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDio sdio = {
|
|
|
|
"usdhc",
|
2022-06-18 12:45:39 +00:00
|
|
|
usdhcinit,
|
|
|
|
usdhcenable,
|
|
|
|
usdhcinquiry,
|
|
|
|
usdhccmd,
|
|
|
|
usdhciosetup,
|
|
|
|
usdhcio,
|
2022-06-14 23:53:03 +00:00
|
|
|
};
|