imx8: port usdhc driver (from bcm/sdhc) for external sdcard
this is a total hack, only works up to 25MHz for now.
This commit is contained in:
cinap_lenrek
parent
176206fb02
commit
28f3dc8224
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@ -7,6 +7,9 @@ enum {
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IRQcntps = PPI+13,
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IRQcntpns = PPI+14,
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IRQusdhc1 = SPI+22,
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IRQusdhc2 = SPI+23,
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IRQuart1 = SPI+26,
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IRQuart2 = SPI+27,
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IRQuart3 = SPI+28,
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@ -19,6 +19,7 @@ dev
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uart
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usb
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i2c
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sd
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link
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usbxhciimx
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@ -36,12 +37,13 @@ ip
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ipmux
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misc
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ccm
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gic
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gpc
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gpio
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gic
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uartimx
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lcd
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uartimx
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iomux
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sdmmc usdhc
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port
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int cpuserver = 0;
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bootdir
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530
sys/src/9/imx8/usdhc.c
Normal file
530
sys/src/9/imx8/usdhc.c
Normal file
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@ -0,0 +1,530 @@
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/sd.h"
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#define USDHC1 (VIRTIO+0xB40000)
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#define USDHC2 (VIRTIO+0xB50000)
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#define EMMCREGS USDHC2
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enum {
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Initfreq = 400000, /* initialisation frequency for MMC */
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SDfreq = 25*Mhz, /* standard SD frequency */
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DTO = 14, /* data timeout exponent (guesswork) */
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GoIdle = 0, /* mmc/sdio go idle state */
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MMCSelect = 7, /* mmc/sd card select command */
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Setbuswidth = 6, /* mmc/sd set bus width command */
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Switchfunc = 6, /* mmc/sd switch function command */
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Voltageswitch = 11, /* md/sdio switch to 1.8V */
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IORWdirect = 52, /* sdio read/write direct command */
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IORWextended = 53, /* sdio read/write extended command */
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Appcmd = 55, /* mmc/sd application command prefix */
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};
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enum {
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/* Controller registers */
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SDMAaddr = 0x00>>2,
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Blksizecnt = 0x04>>2,
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Arg1 = 0x08>>2,
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Cmdtm = 0x0c>>2,
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Resp0 = 0x10>>2,
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Resp1 = 0x14>>2,
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Resp2 = 0x18>>2,
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Resp3 = 0x1c>>2,
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Data = 0x20>>2,
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Status = 0x24>>2,
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Control0 = 0x28>>2,
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Control1 = 0x2c>>2,
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Interrupt = 0x30>>2,
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Irptmask = 0x34>>2,
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Irpten = 0x38>>2,
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Control2 = 0x3c>>2,
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Capability = 0x40>>2,
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Mixctrl = 0x48>>2,
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Forceirpt = 0x50>>2,
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Dmadesc = 0x58>>2,
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Vendorspec = 0xC0>>2,
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/* Vendorspec */
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ClkEn = 1<<14,
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PerEn = 1<<13,
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HclkEn = 1<<12,
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IpgEn = 1<<11,
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Vsel = 1<<1,
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/* Control0 (PROT_CTRL) */
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Dmaselect = 3<<8,
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DmaSDMA = 0<<8,
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DmaADMA1 = 1<<8,
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DmaADMA2 = 2<<8,
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BE = 0<<4,
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HBE = 1<<4,
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LE = 2<<4,
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DwidthMask = 3<<1,
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Dwidth8 = 2<<1,
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Dwidth4 = 1<<1,
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Dwidth1 = 0<<1,
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LED = 1<<0,
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/* Control1 (SYS_CTRL) */
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Srstdata = 1<<26, /* reset data circuit */
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Srstcmd = 1<<25, /* reset command circuit */
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Srsthc = 1<<24, /* reset complete host controller */
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Datatoshift = 16, /* data timeout unit exponent */
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Datatomask = 0xF0000,
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SDCLKFSshift = 8,
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DVSshift = 4,
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/* Cmdtm */
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Indexshift = 24,
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Suspend = 1<<22,
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Resume = 2<<22,
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Abort = 3<<22,
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Isdata = 1<<21,
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Ixchken = 1<<20,
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Crcchken = 1<<19,
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Respmask = 3<<16,
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Respnone = 0<<16,
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Resp136 = 1<<16,
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Resp48 = 2<<16,
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Resp48busy = 3<<16,
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/* Mixctrl */
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Autocmd23 = 1<<7,
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Multiblock = 1<<5,
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Host2card = 0<<4,
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Card2host = 1<<4,
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DdrEn = 1<<3,
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Autocmd12 = 1<<2,
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Blkcnten = 1<<1,
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Dmaen = 1<<0,
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MixCmdMask = 0xFF ^ DdrEn,
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/* Interrupt */
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Admaerr = 1<<28,
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Acmderr = 1<<24,
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Denderr = 1<<22,
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Dcrcerr = 1<<21,
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Dtoerr = 1<<20,
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Cbaderr = 1<<19,
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Cenderr = 1<<18,
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Ccrcerr = 1<<17,
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Ctoerr = 1<<16,
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Err = Admaerr|Acmderr|Denderr|Dcrcerr|Dtoerr|Cbaderr|Cenderr|Ccrcerr|Ctoerr,
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Cardintr = 1<<8,
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Cardinsert = 1<<6,
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Readrdy = 1<<5,
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Writerdy = 1<<4,
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Dmaintr = 1<<3,
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Datadone = 1<<1,
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Cmddone = 1<<0,
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/* Status */
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Bufread = 1<<11,
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Bufwrite = 1<<10,
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Readtrans = 1<<9,
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Writetrans = 1<<8,
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Clkstable = 1<<3,
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Datactive = 1<<2,
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Datinhibit = 1<<1,
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Cmdinhibit = 1<<0,
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};
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static int cmdinfo[64] = {
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[0] Ixchken,
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[2] Resp136,
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[3] Resp48 | Ixchken | Crcchken,
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[5] Resp48,
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[6] Resp48 | Ixchken | Crcchken,
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[7] Resp48 | Ixchken | Crcchken,
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[8] Resp48 | Ixchken | Crcchken,
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[9] Resp136,
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[11] Resp48 | Ixchken | Crcchken,
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[12] Resp48busy | Ixchken | Crcchken,
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[13] Resp48 | Ixchken | Crcchken,
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[16] Resp48,
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[17] Resp48 | Isdata | Card2host | Ixchken | Crcchken,
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[18] Resp48 | Isdata | Card2host | Multiblock | Blkcnten | Ixchken | Crcchken | Autocmd12,
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[24] Resp48 | Isdata | Host2card | Ixchken | Crcchken,
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[25] Resp48 | Isdata | Host2card | Multiblock | Blkcnten | Ixchken | Crcchken | Autocmd12,
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[41] Resp48,
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[52] Resp48 | Ixchken | Crcchken,
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[53] Resp48 | Ixchken | Crcchken | Isdata,
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[55] Resp48 | Ixchken | Crcchken,
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};
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typedef struct Adma Adma;
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typedef struct Ctlr Ctlr;
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/*
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* ADMA2 descriptor
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* See SD Host Controller Simplified Specification Version 2.00
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*/
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struct Adma {
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u32int desc;
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u32int addr;
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};
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enum {
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/* desc fields */
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Valid = 1<<0,
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End = 1<<1,
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Int = 1<<2,
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Nop = 0<<4,
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Tran = 2<<4,
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Link = 3<<4,
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OLength = 16,
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/* maximum value for Length field */
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Maxdma = 1<<12,
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};
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struct Ctlr {
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Rendez r;
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int fastclock;
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uint extclk;
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int appcmd;
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Adma *dma;
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};
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static Ctlr emmc;
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static void mmcinterrupt(Ureg*, void*);
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static void
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WR(int reg, u32int val)
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{
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u32int *r = (u32int*)EMMCREGS;
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if(0)print("WR %2.2ux %ux\n", reg<<2, val);
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coherence();
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r[reg] = val;
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}
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static Adma*
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dmaalloc(void *addr, int len)
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{
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int n;
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uintptr a;
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Adma *adma, *p;
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a = (uintptr)addr;
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n = (len + Maxdma-1) / Maxdma;
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adma = sdmalloc(n * sizeof(Adma));
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for(p = adma; len > 0; p++){
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p->desc = Valid | Tran;
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if(n == 1)
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p->desc |= len<<OLength | End | Int;
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else
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p->desc |= Maxdma<<OLength;
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p->addr = PADDR(a);
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a += Maxdma;
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len -= Maxdma;
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n--;
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}
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cachedwbse(adma, (char*)p - (char*)adma);
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return adma;
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}
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static void
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emmcclk(uint freq)
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{
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u32int *r = (u32int*)EMMCREGS;
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uint pre_div = 1, post_div = 1, clk = emmc.extclk;
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while(clk / (pre_div * 16) > freq && pre_div < 256)
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pre_div <<= 1;
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while(clk / (pre_div * post_div) > freq && post_div < 16)
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post_div++;
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WR(Vendorspec, r[Vendorspec] & ~ClkEn);
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WR(Control1, (pre_div>>1)<<SDCLKFSshift | (post_div-1)<<DVSshift | DTO<<Datatoshift);
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delay(10);
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WR(Vendorspec, r[Vendorspec] | ClkEn | PerEn);
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while((r[Status] & Clkstable) == 0)
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;
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}
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static int
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datadone(void*)
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{
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int i;
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u32int *r = (u32int*)EMMCREGS;
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i = r[Interrupt];
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return i & (Datadone|Err);
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}
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static int
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emmcinit(void)
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{
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u32int *r = (u32int*)EMMCREGS;
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setclkgate("usdhc2.ipg_clk", 1);
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setclkgate("usdhc2.ipg_clk_perclk", 1);
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emmc.extclk = getclkrate("usdhc2.ipg_clk_perclk");
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if(emmc.extclk <= 0){
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print("emmc: usdhc2.ipg_clk_perclk not enabled\n");
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return -1;
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}
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if(0)print("emmc control %8.8ux %8.8ux %8.8ux\n",
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r[Control0], r[Control1], r[Control2]);
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WR(Control1, Srsthc);
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delay(10);
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while(r[Control1] & Srsthc)
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;
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WR(Control1, Srstdata);
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delay(10);
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WR(Control1, 0);
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return 0;
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}
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static int
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emmcinquiry(char *inquiry, int inqlen)
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{
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return snprint(inquiry, inqlen, "USDHC Host Controller");
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}
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static void
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emmcenable(void)
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{
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u32int *r = (u32int*)EMMCREGS;
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WR(Control0, 0);
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delay(1);
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WR(Vendorspec, r[Vendorspec] & ~Vsel);
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WR(Control0, LE | Dwidth1 | DmaADMA2);
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WR(Control1, 0);
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delay(1);
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WR(Vendorspec, r[Vendorspec] | HclkEn | IpgEn);
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emmcclk(Initfreq);
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WR(Irpten, 0);
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WR(Irptmask, ~(Cardintr|Dmaintr));
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WR(Interrupt, ~0);
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intrenable(IRQusdhc2, mmcinterrupt, nil, BUSUNKNOWN, "usdhc2");
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}
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static int
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emmccmd(u32int cmd, u32int arg, u32int *resp)
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{
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u32int *r = (u32int*)EMMCREGS;
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u32int c;
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int i;
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ulong now;
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/* using Autocmd12 */
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if(cmd == 12)
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return 0;
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assert(cmd < nelem(cmdinfo) && cmdinfo[cmd] != 0);
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c = (cmd << Indexshift) | cmdinfo[cmd];
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/*
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* CMD6 may be Setbuswidth or Switchfunc depending on Appcmd prefix
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*/
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if(cmd == Switchfunc && !emmc.appcmd)
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c |= Isdata|Card2host;
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if(c & Isdata)
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c |= Dmaen;
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if(cmd == IORWextended){
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if(arg & (1<<31))
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c |= Host2card;
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else
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c |= Card2host;
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if((r[Blksizecnt]&0xFFFF0000) != 0x10000)
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c |= Multiblock | Blkcnten;
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}
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/*
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* GoIdle indicates new card insertion: reset bus width & speed
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*/
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if(cmd == GoIdle){
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
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emmcclk(Initfreq);
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}
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if(r[Status] & Cmdinhibit){
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print("emmccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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WR(Control1, r[Control1] | Srstcmd);
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while(r[Control1] & Srstcmd)
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;
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while(r[Status] & Cmdinhibit)
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;
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}
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if((r[Status] & Datinhibit) &&
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((c & Isdata) || (c & Respmask) == Resp48busy)){
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print("emmccmd: need to reset Datinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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WR(Control1, r[Control1] | Srstdata);
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while(r[Control1] & Srstdata)
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;
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while(r[Status] & Datinhibit)
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;
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}
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while(r[Status] & Datactive)
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;
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WR(Arg1, arg);
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if((i = (r[Interrupt] & ~Cardintr)) != 0){
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if(i != Cardinsert)
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print("emmc: before command, intr was %ux\n", i);
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WR(Interrupt, i);
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}
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WR(Mixctrl, (r[Mixctrl] & ~MixCmdMask) | (c & MixCmdMask));
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WR(Cmdtm, c & ~0xFFFF);
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now = MACHP(0)->ticks;
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while(((i=r[Interrupt])&(Cmddone|Err)) == 0)
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if(MACHP(0)->ticks - now > HZ)
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break;
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if((i&(Cmddone|Err)) != Cmddone){
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if((i&~(Err|Cardintr)) != Ctoerr)
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print("emmc: cmd %ux arg %ux error intr %ux stat %ux\n", c, arg, i, r[Status]);
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WR(Interrupt, i);
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if(r[Status]&Cmdinhibit){
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WR(Control1, r[Control1]|Srstcmd);
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while(r[Control1]&Srstcmd)
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;
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}
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error(Eio);
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}
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WR(Interrupt, i & ~(Datadone|Readrdy|Writerdy));
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switch(c & Respmask){
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case Resp136:
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resp[0] = r[Resp0]<<8;
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resp[1] = r[Resp0]>>24 | r[Resp1]<<8;
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resp[2] = r[Resp1]>>24 | r[Resp2]<<8;
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resp[3] = r[Resp2]>>24 | r[Resp3]<<8;
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break;
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case Resp48:
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case Resp48busy:
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resp[0] = r[Resp0];
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break;
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case Respnone:
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resp[0] = 0;
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break;
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}
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if((c & Respmask) == Resp48busy){
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WR(Irpten, r[Irpten]|Datadone|Err);
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tsleep(&emmc.r, datadone, 0, 1000);
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i = r[Interrupt];
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if((i & Datadone) == 0)
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print("emmcio: no Datadone in %x after CMD%d\n", i, cmd);
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if(i & Err)
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print("emmcio: CMD%d error interrupt %ux\n",
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cmd, r[Interrupt]);
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if(i != 0) WR(Interrupt, i);
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}
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/*
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* Once card is selected, use faster clock
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*/
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if(cmd == MMCSelect){
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emmcclk(SDfreq);
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emmc.fastclock = 1;
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}
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if(cmd == Setbuswidth){
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if(emmc.appcmd){
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/*
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* If card bus width changes, change host bus width
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*/
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switch(arg){
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case 0:
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
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||||
break;
|
||||
case 2:
|
||||
WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}else if(cmd == IORWdirect && (arg & ~0xFF) == (1<<31|0<<28|7<<9)){
|
||||
switch(arg & 0x3){
|
||||
case 0:
|
||||
WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
|
||||
break;
|
||||
case 2:
|
||||
WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
emmc.appcmd = (cmd == Appcmd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
emmciosetup(int write, void *buf, int bsize, int bcount)
|
||||
{
|
||||
int len;
|
||||
|
||||
len = bsize * bcount;
|
||||
assert(((uintptr)buf&3) == 0);
|
||||
assert((len&3) == 0);
|
||||
assert(bsize <= 2048);
|
||||
WR(Blksizecnt, bcount<<16 | bsize);
|
||||
if(emmc.dma)
|
||||
sdfree(emmc.dma);
|
||||
emmc.dma = dmaalloc(buf, len);
|
||||
if(write)
|
||||
cachedwbse(buf, len);
|
||||
else
|
||||
cachedwbinvse(buf, len);
|
||||
WR(Dmadesc, PADDR(emmc.dma));
|
||||
}
|
||||
|
||||
static void
|
||||
emmcio(int write, uchar *buf, int len)
|
||||
{
|
||||
u32int *r = (u32int*)EMMCREGS;
|
||||
int i;
|
||||
|
||||
WR(Irpten, r[Irpten] | Datadone|Err);
|
||||
tsleep(&emmc.r, datadone, 0, 3000);
|
||||
WR(Irpten, r[Irpten] & ~(Datadone|Err));
|
||||
i = r[Interrupt];
|
||||
if((i & (Datadone|Err)) != Datadone){
|
||||
print("sdhc: %s error intr %ux stat %ux\n",
|
||||
write? "write" : "read", i, r[Status]);
|
||||
WR(Interrupt, i);
|
||||
error(Eio);
|
||||
}
|
||||
WR(Interrupt, i);
|
||||
if(!write)
|
||||
cachedinvse(buf, len);
|
||||
}
|
||||
|
||||
static void
|
||||
mmcinterrupt(Ureg*, void*)
|
||||
{
|
||||
u32int *r;
|
||||
int i;
|
||||
|
||||
r = (u32int*)EMMCREGS;
|
||||
i = r[Interrupt];
|
||||
if(i&(Datadone|Err))
|
||||
wakeup(&emmc.r);
|
||||
WR(Irpten, r[Irpten] & ~i);
|
||||
}
|
||||
|
||||
SDio sdio = {
|
||||
"usdhc",
|
||||
emmcinit,
|
||||
emmcenable,
|
||||
emmcinquiry,
|
||||
emmccmd,
|
||||
emmciosetup,
|
||||
emmcio,
|
||||
};
|
||||
Loading…
Reference in a new issue