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CORE-16748 - Display the correct TR register value. - Ensure that the x86 segment register values displayed are really 2-byte long. Segment registers are intrinsically 16 bits. Even if the x86 KTRAP_FRAME structure stores them as ULONG, only their lower 16 bits are initialized. We thus cast them to USHORT before display. These segment registers are saved in a stack-based KTRAP_FRAME by the CPU trap mechanism (for SS), and by 'push CS' etc. instructions for the others, and from Intel documentation, we know that: " If the source operand is a segment register (16 bits) and the operand size is 64-bits, a zero-extended value is pushed on the stack; if the operand size is 32-bits, either a zero-extended value is pushed on the stack or the segment selector is written on the stack using a 16-bit move. For the last case, all recent Core and Atom processors perform a 16-bit move, leaving the upper portion of the stack location unmodified. " So it may happen, when using the push, that either they get zero-extended, or garbage gets stored in the higher bits, and these need to be trimmed. |
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