fix pch support, with proper dependancies.
Use cmake built-in functions instead of doing weird "magic" with tabs and spaces.
According to gcc doc, if header.h is precompiled, the output should be named "header.h.gch" and not anything else.
svn path=/trunk/; revision=52058
- Inform the PnP manager that we don't support stopping devices by failing the IRP_MN_QUERY_STOP_DEVICE IRP instead of the IRP_MN_STOP_DEVICE IRP (which is not allowed)
svn path=/trunk/; revision=51928
All dlls and drivers are in their normal directories instead of having all in reactos\.
Original implementation by zefklop in cmake branch.
svn path=/trunk/; revision=51830
- Fix PciGetHackFlags for setup found by sir_richard "Setup currently doesn't have a correct registry"
- Fix DriverEntry for setup like PciGetHackFlags
- Fix DriverEntry PciOpenKey check found by sir_richard "PciOpenKey returns a BOOLEAN, not an NTSTATUS"
- Stop call PciGetAcpiTable found by sir_richard "PciGetAcpiTable is really broken, can lead to infinite loops, and also corrupts memory. We need to fix stefan's bugs"
- Implement not root FDO code in PciScanBus and support PCI_HACK_ONE_CHILD
- Implement multiple FDO exist code in PciAddDevice so PCI Bridge support now
- Implement PciAreBusNumbersConfigured for PCI Bridge support
- Hack FDO Start Device by sir_richard "The root FDO does send boot resources if PCIX is installed properly, this code will be needed"
- Do PCI_BUS_DRIVER_INTERNAL bugcheck by sir_richard "I have hacked KeBugCheckEx to ignore this for now, until PnP is fixed"
- Implement not root FDO code in PciInitializeArbiters
- Implement PciCacheLegacyDeviceRouting, PciFindPdoByLocation used by PciAssignSlotResources
- Make PciTranslateBusAddress do the stub work
- PciAssignSlotResources disabled because ReactOS not support IoAssignResources
- Implement PPBridge_ChangeResourceSettings
PCIX driver nearly working now.
svn path=/trunk/; revision=48851
- Part support for resource change with PciComputeNewCurrentSettings... full support for PciSetResources, PciUpdateHardware, PcipUpdateHardare
- IRP_MN_START_DEVICE for PDO (PciPdoIrpStartDevice) implement
- PciNextPartialDescriptor, PciDebugPrintCmResList, PciDebugPrintPartialResource helpers implement
- Now full PDO support almost done, PCIX driver ready for test
- Thanks to cgoodman assert fix
- PnP forever recursion in enumerate, must fix to finish
- Goodbye sir_richard, nice to have you
svn path=/trunk/; revision=48748
- Do all of the work inside the DPC so we don't have IRQL issues when entering the memory manager
- This is a slight hack but we can be assured that data won't be over 24 bits unless somebody wants to push the power/sleep button over 16 million times
svn path=/trunk/; revision=48573
- Debug helpers: PciDebugPrintIoResReqList, PciDebugPrintIoResource, PciDebugCmResourceTypeToText
Now hit assert Assertion '(DeviceNode->Flags & DNF_ADDED)' failed at ntoskrnl/io/pnpmgr/pnpmgr.c line 201, too night to debug, maybe tomorow
svn path=/trunk/; revision=48550
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
PciScanBus second pass enabled: PciProcessBus, most stubs now until VGA/ISA system tested
PciClassifyDeviceType implement as helper function
PCI Enumeration 100% complete!
svn path=/trunk/; revision=48492
More support ICH0/1/2/3/4 hub
Add all PCI2PCI bridge limit/current resource codes (PPBridge_*), now is BAR setup okay, and Device_* must be implement
Support ISA+VGA legacy decode, 20+64-bit decode, ROM BAR, prefetch BAR
svn path=/trunk/; revision=48298
PcipGetfunctionLimits support PCI_HACK_CRITICAL_DEVICE and PCI Debug Device by use IPI code (PciExecuteCriticalSystemRoutine implement)
PciConfigurators table define for Device, PCI-to-PCI (PP) Bridge plus CardBus Bridge but all configurator stub now
Configurator chain: Init (Massage) -> [WRITE INIT] (PciWriteLimitsAndRestoreCurrent) -> Restore -> SaveLimit -> SaveCurrent
Support ExpectedWritebackFailure
Fix bug in PciApplyHacks (found by me testing sir_richard code)
Now pass 7000 SLOC ^_^;~ Good night!
svn path=/trunk/; revision=48118
By sir_richard: [PCIX]: - Implement PciIsSlotPresentInParentMethod for ACPI query, and PcoDecodeEnable utility function.
- Implement PciConfigureIdeController based on WDHC Whitepaper "How Windows Switches a Controller to Native Mode". Check for PciEanbleNativeModeATA in registry, InitSafeBootMode, and call the ACPI driver to evaluate if NATA is present on the slot. Only configure the controller if both channels support native mode, as this is a Windows restriction.
- Implement PciApplyHacks for enumeration and resource update cases. In the first case, we handle legacy DEC Alpha Intel i82375 and i82378 PCI-to-(E)ISA bridges with invalid class codes. In the second, we configure IDE controllers for Native mode, except the OPTi Viper-M, which is known to cause issues. We also support cards with legacy VGA decodes by telling the arbiter to enable full access to the rangesm and finally we completely disable the decodes on Compaq PCI Hotplug Controllers (Revision 17) on PAE systems, as they have bugs handling 64-bit addresses. Finally, on resource updates, we apply a vendor-specific errata to the IBM 20H2999 PCI Docking Bridge (Hotplug) used on Thinkpad 600 Series laptops, and we attempt to avoid issues that can happen on certain devices that are plugged into an ICH1/2/3/4 Intel Hub when it has been configured to do subtractive decode. Full information on these workarounds can be seen in the comments. Finally, we also enable CardBUS devices for ACPI-compliant mode, by crossing out the LegacyBaseAddress in the CardBUS Type 2 PCI Configuration Header.
- Miscelleaneous code cleanups.
By eVb: More PciScanBus support, for debug PCI caps that driver use are dump, and detect nonBIOS configure device (spec is said that CacheLineSize != 0, LatencyTimer != 0 (on PCI-X, != 64)), if found NeedsHotPlugConfiguration to be set
By eVb: Support PCI_HACK_VIDEO_LEGACY_DECODE (call ario_ApplyBrokenVideoHack, but no arb support to do work)
svn path=/trunk/; revision=48116
Support PCI_HACK_NO_PM_CAPS, PCI_HACK_PRESERVE_COMMAND, PCI_HACK_DONT_DISABLE_DECOES
Add scan bus function to set power for PCI, for now to power up (PciSetPowerManagedDevicePowerState), with support for device that is critical/broken (PciCanDisableDecodes)
Check spec-correct with PciStallForPowerChange after define PciPowerDelayTable for D0<->D3 crossmatrix spec timings (add PciReadDeviceConfig for support)
If bad spec timing use PCI verifier support (PciVerifierRetrieveFailureData) + STATUS_DEVICE_PROTOCOL_ERROR
Add PciVerifierFailureTable with all failure type
Almost the time for resource discovery of BARs!
svn path=/trunk/; revision=48107
Also for interrupt line use HAL to get parent bus IRQ# if device connected (PciGetAdjustedInterruptLine)
For PCI debug HW PciIsDeviceOnDebugPath to detect, but have not real machine with this kind of device to test
Support PCI_HACK_NO_SUBSYSTEM and PCI_HACK_NO_SUBSYSTEM/REVISION_AFTER_D3 for when compareing
New config function required PciWriteDeviceConfig to update IRQ line from BIOS registry data
Save initial, current Command enables to PDO extension, interrupt data too
svn path=/trunk/; revision=48100
Fix bug in PciFindPdoByFunction should check device slot info too
Add more enumeration codes in PciScanBus to create PDO
PCI_HACK_FAKE_CLASS_CODE support
Build PDO extension, set ready for PnP manger, now 41 QDR returned
Add PCI/CardBus Bridge to list
Detect bridge/IDE controller with no power down support, hack for Intel 82375 PCI to EISA bridge for Alpha thanks to sir_richard
QUERY_ID is sent to PDOs now!
svn path=/trunk/; revision=48099
Do check for skipping some function (double decker ghost, Intel Alder SMP Pentium Pro machine, hacl flag, more), PciSkipThisfunction
Do check for PDO already exist for function (PciFindPdoByFunction)
Finish impement PciFindParentPciFdoExtension
svn path=/trunk/; revision=48098
Add PDO_EXTENSION structure and PCI_FUNCTION_RESOURCES, now delete #if0 in old code since PDO_EXTENSION is now exist defintion
Add ID Class/Subclass to description functions (PciGetDeviceDescriptionMessage, PciGetDescriptionMessage), use pciclass.mc from sir_richard
New debug: PciDebugDumpCommonConfig
Implement IRP_MN_QUERY_DEVICE_RELATIONS with PciFdoIrpQueryDeviceRelations and PciQueryDeviceRelations
Begin PciScanBus, now just dump all found device with no more work (0 QDR return)
svn path=/trunk/; revision=48091
PciInitializeArbiterRanges implement to scan arbiter not yet construct since Arb library missing
Add PCI state machine (PciBeginStateTransition, PciCancelStateTransition, PciCommitStateTransition) andtransition array (PnpStateTransitionArray) to check if valid
Now IRP_MN_QUERY_DEVICE_RELATIONS sent to ROOT FDO means time to enumerate bus!
svn path=/trunk/; revision=48075
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
- Create a resource list for the PCI root bus (even though it doesn't use any resources according to ACPI) and fill it with a bus number resource descriptor
- Fixes PCI device detection with ACPI enabled
svn path=/trunk/; revision=47729
- Add some missing NTAPI
- Fix AcpiInterfaceConnectVector and AcpiInterfaceDisconnectVector parameters (ACPI_INTERFACE_STANDARD version 1 not version 2)
- Patch by Amine Khaldi
svn path=/trunk/; revision=47489
- Store correct bus and slot information in resource lists that we give in response to IRP_MN_QUERY_RESOURCES and IRP_MN_QUERY_RESOURCE_REQUIREMENTS
- Fixes bug 4354
svn path=/trunk/; revision=47068
- Forward IRPs to our PDO instead of just completing them
- Handle IRP_MN_START_DEVICE on the way back up the stack (allows the PDO code to assign resources to the bus)
- Add some synchronous IRP forwarding copied from i8042prt
svn path=/trunk/; revision=46996
