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Support PCI device resource dicsovery for limit and current now, so bridge + device BAR functionning
PciScanBus second pass enabled: PciProcessBus, most stubs now until VGA/ISA system tested PciClassifyDeviceType implement as helper function PCI Enumeration 100% complete! svn path=/trunk/; revision=48492
This commit is contained in:
evb
parent
f83e778875
commit
55f39ef1a3
4 changed files with 317 additions and 14 deletions
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@ -20,32 +20,238 @@ VOID
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NTAPI
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Device_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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UNIMPLEMENTED;
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while (TRUE);
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PPCI_COMMON_HEADER PciData;
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PIO_RESOURCE_DESCRIPTOR IoDescriptor;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
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PPCI_FUNCTION_RESOURCES Resources;
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PULONG BarArray;
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ULONG Bar, BarMask, i;
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/* Get variables from context */
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PciData = Context->Current;
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Resources = Context->PdoExtension->Resources;
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/* Loop all the PCI BARs */
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BarArray = PciData->u.type0.BaseAddresses;
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for (i = 0; i <= PCI_TYPE0_ADDRESSES; i++)
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{
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/* Get the resource descriptor and limit descriptor for this BAR */
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CmDescriptor = &Resources->Current[i];
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IoDescriptor = &Resources->Limit[i];
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/* Build the resource descriptor based on the limit descriptor */
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CmDescriptor->Type = IoDescriptor->Type;
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if (CmDescriptor->Type == CmResourceTypeNull) continue;
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CmDescriptor->Flags = IoDescriptor->Flags;
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CmDescriptor->ShareDisposition = IoDescriptor->ShareDisposition;
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CmDescriptor->u.Generic.Start.HighPart = 0;
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CmDescriptor->u.Generic.Length = IoDescriptor->u.Generic.Length;
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/* Read the actual BAR value */
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Bar = BarArray[i];
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/* Check which BAR is being processed now */
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if (i != PCI_TYPE0_ADDRESSES)
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{
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/* Check if this is an I/O BAR */
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if (Bar & PCI_ADDRESS_IO_SPACE)
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{
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/* Use the right mask to get the I/O port base address */
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ASSERT(CmDescriptor->Type == CmResourceTypePort);
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BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
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}
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else
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{
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/* It's a RAM BAR, use the right mask to get the base address */
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ASSERT(CmDescriptor->Type == CmResourceTypeMemory);
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BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
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/* Check if it's a 64-bit BAR */
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if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
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{
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/* The next BAR value is actually the high 32-bits */
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CmDescriptor->u.Memory.Start.HighPart = BarArray[i + 1];
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}
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else if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
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{
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/* Legacy BAR, don't read more than 20 bits of the address */
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BarMask = 0xFFFF0;
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}
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}
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}
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else
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{
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/* Actually a ROM BAR, so read the correct register */
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Bar = PciData->u.type0.ROMBaseAddress;
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/* Apply the correct mask for ROM BARs */
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BarMask = PCI_ADDRESS_ROM_ADDRESS_MASK;
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/* Make sure it's enabled */
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if (!(Bar & PCI_ROMADDRESS_ENABLED))
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{
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/* If it isn't, then a descriptor won't be built for it */
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CmDescriptor->Type = CmResourceTypeNull;
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continue;
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}
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}
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/* Now we have the right mask, read the actual address from the BAR */
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Bar &= BarMask;
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CmDescriptor->u.Memory.Start.LowPart = Bar;
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/* And check for invalid BAR addresses */
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if (!(CmDescriptor->u.Memory.Start.HighPart | Bar))
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{
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/* Skip these descriptors */
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CmDescriptor->Type = CmResourceTypeNull;
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DPRINT1("Invalid BAR\n");
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}
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}
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/* Also save the sub-IDs that came directly from the PCI header */
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Context->PdoExtension->SubsystemVendorId = PciData->u.type0.SubVendorID;
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Context->PdoExtension->SubsystemId = PciData->u.type0.SubSystemID;
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}
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VOID
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NTAPI
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Device_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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UNIMPLEMENTED;
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while (TRUE);
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PPCI_COMMON_HEADER Current, PciData;
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PPCI_PDO_EXTENSION PdoExtension;
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PULONG BarArray;
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PIO_RESOURCE_DESCRIPTOR Limit;
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ULONG i;
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/* Get pointers from the context */
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PdoExtension = Context->PdoExtension;
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Current = Context->Current;
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PciData = Context->PciData;
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/* And get the array of bARs */
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BarArray = PciData->u.type0.BaseAddresses;
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/* First, check for IDE controllers that are not in native mode */
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if ((PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
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(PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR) &&
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(PdoExtension->ProgIf & 5) != 5)
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{
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/* They should not be using any non-legacy resources */
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BarArray[0] = 0;
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BarArray[1] = 0;
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BarArray[2] = 0;
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BarArray[3] = 0;
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}
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else if ((PdoExtension->VendorId == 0x5333) &&
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((PdoExtension->DeviceId == 0x88F0) ||
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(PdoExtension->DeviceId == 0x8880)))
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{
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/*
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* The problem is caused by the S3 Vision 968/868 video controller which
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* is used on the Diamond Stealth 64 Video 3000 series, Number Nine 9FX
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* motion 771, and other popular video cards, all containing a memory bug.
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* The 968/868 claims to require 32 MB of memory, but it actually decodes
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* 64 MB of memory.
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*/
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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/* Find its 32MB RAM BAR */
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if (BarArray[i] == 0xFE000000)
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{
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/* Increase it to 64MB to make sure nobody touches the buffer */
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BarArray[i] = 0xFC000000;
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DPRINT1("PCI - Adjusted broken S3 requirement from 32MB to 64MB\n");
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}
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}
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}
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/* Check for Cirrus Logic GD5430/5440 cards */
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if ((PdoExtension->VendorId == 0x1013) && (PdoExtension->DeviceId == 0xA0))
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{
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/* Check for the I/O port requirement */
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if (BarArray[1] == 0xFC01)
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{
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/* Check for completely bogus BAR */
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if (Current->u.type0.BaseAddresses[1] == 1)
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{
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/* Ignore it */
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BarArray[1] = 0;
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DPRINT1("PCI - Ignored Cirrus GD54xx broken IO requirement (400 ports)\n");
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}
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else
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{
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/* Otherwise, this BAR seems okay */
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DPRINT1("PCI - Cirrus GD54xx 400 port IO requirement has a valid setting (%08x)\n",
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Current->u.type0.BaseAddresses[1]);
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}
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}
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else if (BarArray[1])
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{
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/* Strange, the I/O BAR was not found as expected (or at all) */
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DPRINT1("PCI - Warning Cirrus Adapter 101300a0 has unexpected resource requirement (%08x)\n",
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BarArray[1]);
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}
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}
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/* Finally, process all the limit descriptors */
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Limit = PdoExtension->Resources->Limit;
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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/* And build them based on the BARs */
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if (PciCreateIoDescriptorFromBarLimit(&Limit[i], &BarArray[i], FALSE))
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{
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/* This function returns TRUE if the BAR was 64-bit, handle this */
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ASSERT((i + 1) < PCI_TYPE0_ADDRESSES);
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i++;
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(&Limit[i])->Type == CmResourceTypeNull;
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}
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}
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/* Create the last descriptor based on the ROM address */
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PciCreateIoDescriptorFromBarLimit(&Limit[i],
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&PciData->u.type0.ROMBaseAddress,
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TRUE);
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}
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VOID
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NTAPI
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Device_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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UNIMPLEMENTED;
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while (TRUE);
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PPCI_COMMON_HEADER PciData;
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PPCI_PDO_EXTENSION PdoExtension;
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PULONG BarArray;
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ULONG i = 0;
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/* Get pointers from context data */
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PdoExtension = Context->PdoExtension;
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PciData = Context->PciData;
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/* Get the array of BARs */
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BarArray = PciData->u.type0.BaseAddresses;
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/* Check for IDE controllers that are not in native mode */
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if ((PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
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(PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR) &&
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(PdoExtension->ProgIf & 5) != 5)
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{
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/* These controllers only use legacy resources */
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i = 4;
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}
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/* Set all the bits on, which will allow us to recover the limit data */
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++) BarArray[i] = 0xFFFFFFFF;
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/* Do the same for the PCI ROM BAR */
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PciData->u.type0.ROMBaseAddress = PCI_ADDRESS_ROM_ADDRESS_MASK;
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}
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VOID
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NTAPI
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Device_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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UNIMPLEMENTED;
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while (TRUE);
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/* Nothing to do for devices */
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return;
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}
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VOID
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@ -54,6 +260,7 @@ Device_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context,
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IN PPCI_COMMON_HEADER PciData,
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IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)
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{
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/* Not yet implemented */
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UNIMPLEMENTED;
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while (TRUE);
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}
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@ -62,6 +269,7 @@ VOID
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NTAPI
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Device_ResetDevice(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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/* Not yet implemented */
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UNIMPLEMENTED;
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while (TRUE);
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}
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@ -70,6 +278,7 @@ VOID
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NTAPI
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Device_ChangeResourceSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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/* Not yet implemented */
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UNIMPLEMENTED;
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while (TRUE);
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}
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@ -32,7 +32,7 @@ PCI_CONFIGURATOR PciConfigurators[] =
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PPBridge_SaveCurrentSettings,
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PPBridge_ChangeResourceSettings,
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PPBridge_GetAdditionalResourceDescriptors,
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PPBridge_ResetDevice
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PPBridge_ResetDevice
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},
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{
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Cardbus_MassageHeaderForLimitsDetermination,
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@ -44,7 +44,7 @@ PCI_CONFIGURATOR PciConfigurators[] =
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Cardbus_ResetDevice
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}
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};
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/* FUNCTIONS ******************************************************************/
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/*
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@ -715,10 +715,10 @@ PciWriteLimitsAndRestoreCurrent(IN PVOID Reserved,
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/* Write the limit discovery header */
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PciWriteDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
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/* Now read what the device indicated the limits are */
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PciReadDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
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/* Then write back the original configuration header */
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PciWriteDeviceConfig(PdoExtension, Current, 0, PCI_COMMON_HDR_LENGTH);
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@ -735,7 +735,7 @@ PciWriteLimitsAndRestoreCurrent(IN PVOID Reserved,
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/* Copy back the original status that was saved as well */
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Current->Status = Context->Status;
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/* Call the configurator to restore any other data that might've changed */
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Context->Configurator->RestoreCurrent(Context);
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}
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@ -917,6 +917,62 @@ PciGetFunctionLimits(IN PPCI_PDO_EXTENSION PdoExtension,
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return Status;
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}
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VOID
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NTAPI
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PciProcessBus(IN PPCI_FDO_EXTENSION DeviceExtension)
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{
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PPCI_PDO_EXTENSION PdoExtension;
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PDEVICE_OBJECT PhysicalDeviceObject;
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PAGED_CODE();
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/* Get the PDO Extension */
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PhysicalDeviceObject = DeviceExtension->PhysicalDeviceObject;
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PdoExtension = (PPCI_PDO_EXTENSION)PhysicalDeviceObject->DeviceExtension;
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/* Cheeck if this is the root bus */
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if (!PCI_IS_ROOT_FDO(DeviceExtension))
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{
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/* Not really handling this year */
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UNIMPLEMENTED;
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while (TRUE);
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/* Check for PCI bridges with the ISA bit set, or required */
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if ((PdoExtension) &&
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(PciClassifyDeviceType(PdoExtension) == PciTypePciBridge) &&
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((PdoExtension->Dependent.type1.IsaBitRequired) ||
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(PdoExtension->Dependent.type1.IsaBitSet)))
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{
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/* We'll need to do some legacy support */
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UNIMPLEMENTED;
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while (TRUE);
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}
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}
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else
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{
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/* Scan all of the root bus' children bridges */
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for (PdoExtension = DeviceExtension->ChildBridgePdoList;
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PdoExtension;
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PdoExtension = PdoExtension->NextBridge)
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{
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/* Find any that have the VGA decode bit on */
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if (PdoExtension->Dependent.type1.VgaBitSet)
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{
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/* Again, some more legacy support we'll have to do */
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UNIMPLEMENTED;
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while (TRUE);
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}
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}
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}
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/* Check for ACPI systems where the OS assigns bus numbers */
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if (PciAssignBusNumbers)
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{
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/* Not yet supported */
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UNIMPLEMENTED;
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while (TRUE);
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}
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}
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NTSTATUS
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NTAPI
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PciScanBus(IN PPCI_FDO_EXTENSION DeviceExtension)
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@ -1363,7 +1419,8 @@ PciScanBus(IN PPCI_FDO_EXTENSION DeviceExtension)
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}
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}
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/* Enumeration is completed */
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/* Enumeration completed, do a final pass now that all devices are found */
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if (ProcessFlag) PciProcessBus(DeviceExtension);
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return STATUS_SUCCESS;
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}
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@ -102,6 +102,18 @@ typedef enum _PCI_SIGNATURE
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PciInterface_Location = 'icP?'
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} PCI_SIGNATURE, *PPCI_SIGNATURE;
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//
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// Driver-handled PCI Device Types
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//
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typedef enum _PCI_DEVICE_TYPES
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{
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PciTypeInvalid,
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PciTypeHostBridge,
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PciTypePciBridge,
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PciTypeCardbusBridge,
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PciTypeDevice
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} PCI_DEVICE_TYPES;
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//
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// Device Extension Logic States
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//
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@ -1064,6 +1076,12 @@ PciCanDisableDecodes(
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IN BOOLEAN ForPowerDown
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);
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PCI_DEVICE_TYPES
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NTAPI
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PciClassifyDeviceType(
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IN PPCI_PDO_EXTENSION PdoExtension
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);
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ULONG_PTR
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NTAPI
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PciExecuteCriticalSystemRoutine(
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@ -1607,6 +1625,7 @@ extern PCI_INTERFACE TranslatorInterfaceInterrupt;
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extern PDRIVER_OBJECT PciDriverObject;
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extern PWATCHDOG_TABLE WdTable;
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extern PPCI_HACK_ENTRY PciHackTable;
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extern BOOLEAN PciAssignBusNumbers;
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extern BOOLEAN PciEnableNativeModeATA;
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/* Exported by NTOS, should this go in the NDK? */
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@ -1041,6 +1041,24 @@ PciCanDisableDecodes(IN PPCI_PDO_EXTENSION DeviceExtension,
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return !(HackFlags & PCI_HACK_NO_PM_CAPS);
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}
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PCI_DEVICE_TYPES
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NTAPI
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PciClassifyDeviceType(IN PPCI_PDO_EXTENSION PdoExtension)
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{
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ASSERT(PdoExtension->ExtensionType == PciPdoExtensionType);
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/* Differenriate between devices and bridges */
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if (PdoExtension->BaseClass != PCI_CLASS_BRIDGE_DEV) return PciTypeDevice;
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/* The PCI Bus driver handles only CardBus and PCI bridges (plus host) */
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if (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST) return PciTypeHostBridge;
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if (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) return PciTypePciBridge;
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if (PdoExtension->SubClass == PCI_SUBCLASS_BR_CARDBUS) return PciTypeCardbusBridge;
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/* Any other kind of bridge is treated like a device */
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return PciTypeDevice;
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}
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ULONG_PTR
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NTAPI
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PciExecuteCriticalSystemRoutine(IN ULONG_PTR IpiContext)
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