mirror of
https://github.com/reactos/reactos.git
synced 2024-07-05 04:06:22 +00:00
We now have a good initialization routine for ARM. We call HalInitializeProcessor (TBD) to setup the board, then we configure the PRCB and PCR. We also setup some global CPU variables and setup minimal interrupt support. The rest of the code follows the x86 design (Create initial thread/process).
There's now a cpu.c for ARM as well, and the cache routines are now there. KDCOM APIs were marked as kernel stubs, so the kernel was never linking with kdcom. This has been fixed, and boot now stops in kdcom!KdPortInitializeEx since there's no ARM-compatible code. svn path=/trunk/; revision=32334
This commit is contained in:
ReactOS Portable Systems Group
parent
93970a965e
commit
ed323f3711
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@ -250,6 +250,11 @@ KdPortInitializeEx(
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ULONG divisor;
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UCHAR lcr;
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#ifdef _ARM_
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UNIMPLEMENTED;
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while (TRUE);
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#endif
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if (PortInformation->BaudRate == 0)
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PortInformation->BaudRate = DEFAULT_BAUD_RATE;
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@ -135,6 +135,7 @@ typedef struct _KPRCB
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UCHAR NodeColor;
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UCHAR Spare1;
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ULONG NodeShiftedColor;
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ULONG PcrPage;
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struct _KNODE *ParentNode;
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ULONG MultiThreadProcessorSet;
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struct _KPRCB *MultiThreadSetMaster;
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@ -22,6 +22,11 @@
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#define PCR ((volatile KPCR * const)USPCR)
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#define USERPCR ((volatile KPCR * const)KIPCR)
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//
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// Maximum IRQs
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//
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#define MAXIMUM_VECTOR 16
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//
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// Just read it from the PCR
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//
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@ -46,7 +51,7 @@ typedef struct _KPCR
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{
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ULONG MinorVersion;
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ULONG MajorVersion;
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PKINTERRUPT_ROUTINE InterruptRoutine[16];
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PKINTERRUPT_ROUTINE InterruptRoutine[MAXIMUM_VECTOR];
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PVOID XcodeDispatch;
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ULONG FirstLevelDcacheSize;
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ULONG FirstLevelDcacheFillSize;
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@ -77,6 +82,7 @@ typedef struct _KPCR
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UCHAR CurrentIrql;
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KAFFINITY SetMember;
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struct _KTHREAD *CurrentThread;
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ULONG ReservedVectors;
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KAFFINITY NotMember;
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ULONG SystemReserved[6];
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ULONG DcacheAlignment;
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@ -127,4 +133,17 @@ KeRaiseIrqlToDpcLevel(
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#define KeLowerIrql(NewIrql) KeSwapIrql(NewIrql)
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#define KeRaiseIrql(NewIrql, OldIrql) *(OldIrql) = KeSwapIrql(NewIrql)
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//
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// Cache clean and flush
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//
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VOID
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HalSweepDcache(
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VOID
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);
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VOID
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HalSweepIcache(
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VOID
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);
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#endif
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@ -148,6 +148,31 @@ KeArmInitThreadWithContext(
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IN PCONTEXT Context
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);
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VOID
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KiPassiveRelease(
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VOID
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);
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VOID
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KiApcInterrupt(
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VOID
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);
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#include "mm.h"
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VOID
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KeFillFixedEntryTb(
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IN ARM_PTE Pte,
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IN PVOID Virtual,
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IN ULONG Index
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);
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VOID
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KeFlushTb(
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VOID
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);
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#define KeArchInitThreadWithContext KeArmInitThreadWithContext
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#endif
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117
reactos/ntoskrnl/ke/arm/cpu.c
Normal file
117
reactos/ntoskrnl/ke/arm/cpu.c
Normal file
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@ -0,0 +1,117 @@
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/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: ntoskrnl/ke/arm/cpu.c
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* PURPOSE: Implements routines for ARM CPU support
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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ULONG KeFixedTbEntries;
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ULONG KiDmaIoCoherency;
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/* FUNCTIONS ******************************************************************/
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VOID
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KiFlushSingleTb(IN BOOLEAN Invalid,
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IN PVOID Virtual)
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{
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//
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// Just invalidate it
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//
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KeArmInvalidateTlbEntry(Virtual);
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}
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VOID
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KeFillFixedEntryTb(IN ARM_PTE Pte,
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IN PVOID Virtual,
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IN ULONG Index)
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{
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ARM_LOCKDOWN_REGISTER LockdownRegister;
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ULONG OldVictimCount;
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volatile unsigned long Temp;
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PARM_TRANSLATION_TABLE TranslationTable;
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//
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// Hack for 1MB Section Entries
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//
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Virtual = (PVOID)((ULONG)Virtual & 0xFFF00000);
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//
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// On ARM, we can't set the index ourselves, so make sure that we are not
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// locking down more than 8 entries.
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//
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UNREFERENCED_PARAMETER(Index);
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KeFixedTbEntries++;
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ASSERT(KeFixedTbEntries <= 8);
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//
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// Flush the address
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//
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KiFlushSingleTb(TRUE, Virtual);
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//
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// Read lockdown register and set the preserve bit
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//
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LockdownRegister = KeArmLockdownRegisterGet();
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LockdownRegister.Preserve = TRUE;
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OldVictimCount = LockdownRegister.Victim;
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Map the PTE for this virtual address
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//
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TranslationTable = (PVOID)KeArmTranslationTableRegisterGet().AsUlong;
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT] = Pte;
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//
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// Now force a miss
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//
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Temp = *(PULONG)Virtual;
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//
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// Read lockdown register
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//
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LockdownRegister = KeArmLockdownRegisterGet();
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if (LockdownRegister.Victim == 0)
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{
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//
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// This can only happen on QEMU or broken CPUs since there *has*
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// to have been at least a miss since the system started. For example,
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// QEMU doesn't support TLB lockdown.
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//
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// On these systems, we'll just keep the PTE mapped
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//
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DPRINT1("TLB Lockdown Failure (%p). Running on QEMU?\n", Virtual);
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}
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else
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{
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//
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// Clear the preserve bits
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//
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LockdownRegister.Preserve = FALSE;
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ASSERT(LockdownRegister.Victim == OldVictimCount + 1);
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Clear the PTE
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//
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT].AsUlong = 0;
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}
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}
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VOID
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KeFlushTb(VOID)
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{
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//
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// Flush the entire TLB
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//
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KeArmFlushTlb();
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}
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@ -14,14 +14,10 @@
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/* GLOBALS ********************************************************************/
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KINTERRUPT KxUnexpectedInterrupt;
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BOOLEAN KeIsArmV6;
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ULONG KeFixedTbEntries;
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ULONG KeNumberProcessIds;
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ULONG KeNumberTbEntries;
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VOID HalSweepDcache(VOID);
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VOID HalSweepIcache(VOID);
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#define __ARMV6__ KeIsArmV6
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//
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@ -44,103 +40,6 @@ DebugService(IN ULONG ServiceType,
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arm_kprintf("%s", Buffer);
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}
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VOID
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KiFlushSingleTb(IN BOOLEAN Invalid,
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IN PVOID Virtual)
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{
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//
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// Just invalidate it
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//
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KeArmInvalidateTlbEntry(Virtual);
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}
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VOID
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KeFillFixedEntryTb(IN ARM_PTE Pte,
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IN PVOID Virtual,
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IN ULONG Index)
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{
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ARM_LOCKDOWN_REGISTER LockdownRegister;
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ULONG OldVictimCount;
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volatile unsigned long Temp;
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PARM_TRANSLATION_TABLE TranslationTable;
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//
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// Hack for 1MB Section Entries
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//
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Virtual = (PVOID)((ULONG)Virtual & 0xFFF00000);
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//
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// On ARM, we can't set the index ourselves, so make sure that we are not
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// locking down more than 8 entries.
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//
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UNREFERENCED_PARAMETER(Index);
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KeFixedTbEntries++;
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ASSERT(KeFixedTbEntries <= 8);
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//
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// Flush the address
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//
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KiFlushSingleTb(TRUE, Virtual);
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//
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// Read lockdown register and set the preserve bit
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//
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LockdownRegister = KeArmLockdownRegisterGet();
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LockdownRegister.Preserve = TRUE;
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OldVictimCount = LockdownRegister.Victim;
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Map the PTE for this virtual address
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//
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TranslationTable = (PVOID)KeArmTranslationTableRegisterGet().AsUlong;
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT] = Pte;
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//
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// Now force a miss
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//
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Temp = *(PULONG)Virtual;
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//
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// Read lockdown register
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//
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LockdownRegister = KeArmLockdownRegisterGet();
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if (LockdownRegister.Victim == 0)
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{
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//
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// This can only happen on QEMU or broken CPUs since there *has*
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// to have been at least a miss since the system started. For example,
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// QEMU doesn't support TLB lockdown.
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//
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// On these systems, we'll just keep the PTE mapped
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//
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DPRINT1("TLB Lockdown Failure (%p). Running on QEMU?\n", Virtual);
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}
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else
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{
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//
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// Clear the preserve bits
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//
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LockdownRegister.Preserve = FALSE;
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ASSERT(LockdownRegister.Victim == OldVictimCount + 1);
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Clear the PTE
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//
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT].AsUlong = 0;
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}
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}
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VOID
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KeFlushTb(VOID)
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{
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//
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// Flush the entire TLB
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//
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KeArmFlushTlb();
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}
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VOID
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NTAPI
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KiInitializeKernel(IN PKPROCESS InitProcess,
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@ -151,34 +50,164 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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LARGE_INTEGER PageDirectory;
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PVOID DpcStack;
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PKPCR Pcr;
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ULONG i;
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DPRINT1("%s Process: %p Thread: %p Stack: %p PRCB: %p Number: %d LoaderBlock: %p\n",
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__FUNCTION__, InitProcess, InitThread, IdleStack, Prcb, Number, LoaderBlock);
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/* Initialize the Power Management Support for this PRCB */
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PoInitializePrcb(Prcb);
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//
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// Initialize the platform
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//
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HalInitializeProcessor(Number, LoaderBlock);
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/* Save CPU state */
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KiSaveProcessorControlState(&Prcb->ProcessorState);
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/* Initialize spinlocks and DPC data */
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//
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// Save loader block
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//
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KeLoaderBlock = LoaderBlock;
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//
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// Setup KPRCB
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//
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Prcb->MajorVersion = 1;
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Prcb->MinorVersion = 1;
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Prcb->BuildType = 0;
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#ifndef CONFIG_SMP
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Prcb->BuildType |= PRCB_BUILD_UNIPROCESSOR;
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#endif
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#ifdef DBG
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Prcb->BuildType |= PRCB_BUILD_DEBUG;
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#endif
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Prcb->CurrentThread = InitThread;
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Prcb->NextThread = NULL;
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Prcb->IdleThread = InitThread;
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Prcb->Number = Number;
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Prcb->SetMember = 1 << Number;
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Prcb->PcrPage = LoaderBlock->u.Arm.PcrPage;
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//
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// Initialize spinlocks and DPC data
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//
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KiInitSpinLocks(Prcb, Number);
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/* Check if this is the Boot CPU */
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//
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// Set the PRCB in the processor block
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//
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KiProcessorBlock[(ULONG)Number] = Prcb;
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Pcr = (PKPCR)KeGetPcr();
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//
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// Set processor information
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//
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
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KeFeatureBits = 0;
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KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8);
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KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF);
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//
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// Set stack pointers
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//
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Pcr->InitialStack = IdleStack;
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Pcr->StackLimit = (PVOID)((ULONG_PTR)IdleStack - KERNEL_STACK_SIZE);
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//
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// Check if this is the Boot CPU
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//
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if (!Number)
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{
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/* Set Node Data */
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KeNodeBlock[0] = &KiNode0;
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Prcb->ParentNode = KeNodeBlock[0];
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KeNodeBlock[0]->ProcessorMask = Prcb->SetMember;
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/* Lower to APC_LEVEL */
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KeLowerIrql(APC_LEVEL);
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//
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// Setup the unexpected interrupt
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//
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KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt;
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for (i = 0; i < 4; i++)
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{
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//
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// Copy the template code
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//
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KxUnexpectedInterrupt.DispatchCode[i] = KiInterruptTemplate[i];
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}
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/* Initialize portable parts of the OS */
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//
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// Set DMA coherency
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//
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KiDmaIoCoherency = 0;
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//
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// Sweep D-Cache
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//
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HalSweepDcache();
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}
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//
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// Set all interrupt routines to unexpected interrupts as well
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//
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for (i = 0; i < MAXIMUM_VECTOR; i++)
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{
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//
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// Point to the same template
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//
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Pcr->InterruptRoutine[i] = &KxUnexpectedInterrupt.DispatchCode;
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}
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//
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// Setup profiling
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//
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Pcr->ProfileCount = 0;
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Pcr->ProfileInterval = 0x200000;
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Pcr->StallScaleFactor = 50;
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//
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// Setup software interrupts
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//
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Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease;
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Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt;
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Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt;
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Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) |
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(1 << APC_LEVEL) |
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(1 << DISPATCH_LEVEL) |
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(1 << IPI_LEVEL);
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//
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// Set IRQL and prcessor member/number
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//
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Pcr->CurrentIrql = APC_LEVEL;
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Pcr->SetMember = 1 << Number;
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Pcr->NotMember = -Pcr->SetMember;
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Pcr->Number = Number;
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//
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// Remember our parent
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//
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InitThread->ApcState.Process = InitProcess;
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//
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// Setup the active processor numbers
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//
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KeActiveProcessors |= 1 << Number;
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KeNumberProcessors = Number + 1;
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//
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// Check if this is the boot CPU
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//
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if (!Number)
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{
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//
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// Setup KD
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//
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KdInitSystem(0, LoaderBlock);
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//
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// Cleanup the rest of the processor block array
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//
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for (i = 1; i < MAXIMUM_PROCESSORS; i++) KiProcessorBlock[i] = NULL;
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//
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||||
// Initialize portable parts of the OS
|
||||
//
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KiInitSystem();
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/* Initialize the Idle Process and the Process Listhead */
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//
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// Initialize the Idle Process and the Process Listhead
|
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//
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||||
InitializeListHead(&KiProcessListHead);
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PageDirectory.QuadPart = 0;
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KeInitializeProcess(InitProcess,
|
||||
|
|
@ -190,11 +219,15 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
|
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}
|
||||
else
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||||
{
|
||||
/* FIXME */
|
||||
DPRINT1("SMP Boot support not yet present\n");
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//
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||||
// FIXME
|
||||
//
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||||
DPRINT1("ARM MPCore not supported\n");
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}
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|
||||
/* Setup the Idle Thread */
|
||||
//
|
||||
// Setup the Idle Thread
|
||||
//
|
||||
KeInitializeThread(InitProcess,
|
||||
InitThread,
|
||||
NULL,
|
||||
|
|
@ -209,61 +242,68 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
|
|||
InitThread->Affinity = 1 << Number;
|
||||
InitThread->WaitIrql = DISPATCH_LEVEL;
|
||||
InitProcess->ActiveProcessors = 1 << Number;
|
||||
|
||||
/* HACK for MmUpdatePageDir */
|
||||
|
||||
//
|
||||
// HACK for MmUpdatePageDir
|
||||
//
|
||||
((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess;
|
||||
|
||||
/* Initialize Kernel Memory Address Space */
|
||||
|
||||
//
|
||||
// Initialize Kernel Memory Address Space
|
||||
//
|
||||
MmInit1(MmFreeLdrFirstKrnlPhysAddr,
|
||||
MmFreeLdrLastKrnlPhysAddr,
|
||||
MmFreeLdrLastKernelAddress,
|
||||
NULL,
|
||||
0,
|
||||
4096);
|
||||
|
||||
/* Set basic CPU Features that user mode can read */
|
||||
|
||||
/* Set up the thread-related fields in the PRCB */
|
||||
Prcb->CurrentThread = InitThread;
|
||||
Prcb->NextThread = NULL;
|
||||
Prcb->IdleThread = InitThread;
|
||||
|
||||
/* Initialize the Kernel Executive */
|
||||
|
||||
//
|
||||
// Initialize the Kernel Executive
|
||||
//
|
||||
ExpInitializeExecutive(Number, LoaderBlock);
|
||||
|
||||
/* Only do this on the boot CPU */
|
||||
//
|
||||
// Only do this on the boot CPU
|
||||
//
|
||||
if (!Number)
|
||||
{
|
||||
/* Calculate the time reciprocal */
|
||||
//
|
||||
// Calculate the time reciprocal
|
||||
//
|
||||
KiTimeIncrementReciprocal =
|
||||
KiComputeReciprocal(KeMaximumIncrement,
|
||||
&KiTimeIncrementShiftCount);
|
||||
|
||||
/* Update DPC Values in case they got updated by the executive */
|
||||
//
|
||||
// Update DPC Values in case they got updated by the executive
|
||||
//
|
||||
Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
|
||||
Prcb->MinimumDpcRate = KiMinimumDpcRate;
|
||||
Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
|
||||
|
||||
/* Allocate the DPC Stack */
|
||||
DpcStack = MmCreateKernelStack(FALSE, 0);
|
||||
if (!DpcStack) KeBugCheckEx(NO_PAGES_AVAILABLE, 1, 0, 0, 0);
|
||||
Prcb->DpcStack = DpcStack;
|
||||
}
|
||||
|
||||
/* Raise to Dispatch */
|
||||
//
|
||||
// Raise to Dispatch
|
||||
//
|
||||
KeSwapIrql(DISPATCH_LEVEL);
|
||||
|
||||
/* Set the Idle Priority to 0. This will jump into Phase 1 */
|
||||
//
|
||||
// Set the Idle Priority to 0. This will jump into Phase 1
|
||||
//
|
||||
KeSetPriorityThread(InitThread, 0);
|
||||
|
||||
/* If there's no thread scheduled, put this CPU in the Idle summary */
|
||||
//
|
||||
// If there's no thread scheduled, put this CPU in the Idle summary
|
||||
//
|
||||
KiAcquirePrcbLock(Prcb);
|
||||
if (!Prcb->NextThread) KiIdleSummary |= 1 << Number;
|
||||
KiReleasePrcbLock(Prcb);
|
||||
|
||||
/* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */
|
||||
//
|
||||
// Raise back to HIGH_LEVEL
|
||||
//
|
||||
KeSwapIrql(HIGH_LEVEL);
|
||||
LoaderBlock->Prcb = 0;
|
||||
}
|
||||
|
||||
VOID
|
||||
|
|
|
|||
|
|
@ -62,6 +62,9 @@ GENERATE_ARM_STUB KeUserModeCallback
|
|||
GENERATE_ARM_STUB Kei386EoiHelper
|
||||
GENERATE_ARM_STUB KiCoprocessorError
|
||||
GENERATE_ARM_STUB KiDispatchInterrupt
|
||||
GENERATE_ARM_STUB KiApcInterrupt
|
||||
GENERATE_ARM_STUB KiPassiveRelease
|
||||
GENERATE_ARM_STUB KiInterruptTemplate
|
||||
GENERATE_ARM_STUB KiUnexpectedInterrupt
|
||||
GENERATE_ARM_STUB MmGetPhysicalAddress
|
||||
GENERATE_ARM_STUB NtVdmControl
|
||||
|
|
@ -122,7 +125,6 @@ GENERATE_ARM_STUB MmGetPfnForProcess
|
|||
GENERATE_ARM_STUB MmCreateVirtualMapping
|
||||
GENERATE_ARM_STUB CmpInitializeMachineDependentConfiguration
|
||||
GENERATE_ARM_STUB KeI386VdmInitialize
|
||||
GENERATE_ARM_STUB KdDebuggerInitialize1
|
||||
GENERATE_ARM_STUB MmSetDirtyPage
|
||||
GENERATE_ARM_STUB MmSetCleanPage
|
||||
GENERATE_ARM_STUB MmIsDirtyPage
|
||||
|
|
@ -146,8 +148,6 @@ GENERATE_ARM_STUB RtlInitializeContext
|
|||
GENERATE_ARM_STUB RtlpGetExceptionAddress
|
||||
GENERATE_ARM_STUB RtlDispatchException
|
||||
GENERATE_ARM_STUB DebugService2
|
||||
GENERATE_ARM_STUB KdPortPutByteEx
|
||||
GENERATE_ARM_STUB KdPortInitializeEx
|
||||
GENERATE_ARM_STUB KdpGdbStubInit
|
||||
GENERATE_ARM_STUB KeSwitchKernelStack
|
||||
GENERATE_ARM_STUB MiInitPageDirectoryMap
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@
|
|||
<directory name="arm">
|
||||
<file first="true">boot.s</file>
|
||||
<file>arm_kprintf.c</file>
|
||||
<file>cpu.c</file>
|
||||
<file>kiinit.c</file>
|
||||
<file>stubs_asm.s</file>
|
||||
<file>stubs.c</file>
|
||||
|
|
|
|||
Loading…
Reference in a new issue