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[NTOS]: Another long-lost-promised straggler for Timo. There may be more of these needed, this is what I had done on my disk.
svn path=/trunk/; revision=48288
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@ -813,6 +813,10 @@ MmProbeAndLockPages(IN PMDL Mdl,
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// Assume failure and check for non-mapped pages
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//
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*MdlPages = -1;
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#if (_MI_PAGING_LEVELS >= 3)
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/* Should be checking the PPE and PXE */
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ASSERT(FALSE);
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#endif
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while ((PointerPde->u.Hard.Valid == 0) ||
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(PointerPte->u.Hard.Valid == 0))
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{
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@ -153,6 +153,7 @@ PMMPTE MiSessionLastPte;
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PVOID MiSystemViewStart;
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SIZE_T MmSystemViewSize;
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#if (_MI_PAGING_LEVELS == 2)
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//
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// A copy of the system page directory (the page directory associated with the
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// System process) is kept (double-mapped) by the manager in order to lazily
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@ -161,6 +162,7 @@ SIZE_T MmSystemViewSize;
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//
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PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
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PMMPTE MmSystemPagePtes;
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#endif
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//
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// The system cache starts right after hyperspace. The first few pages are for
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@ -228,6 +230,9 @@ PVOID MmSystemRangeStart;
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/* And these store the respective highest PTE/PDE address */
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PMMPTE MiHighestUserPte;
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PMMPDE MiHighestUserPde;
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#if (_MI_PAGING_LEVELS >= 3)
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/* We need the highest PPE and PXE addresses */
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#endif
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/* These variables define the system cache address space */
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PVOID MmSystemCacheStart;
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@ -1476,7 +1481,7 @@ MiBuildPagedPool(VOID)
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PFN_NUMBER PageFrameIndex;
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KIRQL OldIrql;
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ULONG Size, BitMapSize;
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#if (_MI_PAGING_LEVELS == 2)
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//
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// Get the page frame number for the system page directory
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//
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@ -1502,7 +1507,7 @@ MiBuildPagedPool(VOID)
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ASSERT(PD_COUNT == 1);
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TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0];
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MI_WRITE_VALID_PTE(PointerPte, TempPte);
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#endif
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//
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// Let's get back to paged pool work: size it up.
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// By default, it should be twice as big as nonpaged pool.
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@ -1554,6 +1559,14 @@ MiBuildPagedPool(VOID)
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// So now get the PDE for paged pool and zero it out
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//
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PointerPde = MiAddressToPde(MmPagedPoolStart);
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#if (_MI_PAGING_LEVELS >= 3)
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/* On these systems, there's no double-mapping, so instead, the PPE and PXEs
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* are setup to span the entire paged pool area, so there's no need for the
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* system PD */
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ASSERT(FALSE);
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#endif
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RtlZeroMemory(PointerPde,
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(1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE));
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@ -1573,7 +1586,14 @@ MiBuildPagedPool(VOID)
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PageFrameIndex = MiRemoveZeroPage(0);
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TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
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MI_WRITE_VALID_PTE(PointerPde, TempPte);
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#if (_MI_PAGING_LEVELS >= 3)
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/* Use the PPE of MmPagedPoolStart that was setup above */
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// Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...));
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ASSERT(FALSE);
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#else
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/* Do it this way */
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// Bla = MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT]
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#endif
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/* Initialize the PFN entry for it */
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MiInitializePfnForOtherProcess(PageFrameIndex,
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PointerPde,
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@ -1700,7 +1720,10 @@ MmArmInitSystem(IN ULONG Phase,
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/* Highest PTE and PDE based on the addresses above */
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MiHighestUserPte = MiAddressToPte(MmHighestUserAddress);
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MiHighestUserPde = MiAddressToPde(MmHighestUserAddress);
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#if (_MI_PAGING_LEVELS >= 3)
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/* We need the highest PPE and PXE addresses */
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ASSERT(FALSE);
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#endif
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//
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// Get the size of the boot loader's image allocations and then round
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// that region up to a PDE size, so that any PDEs we might create for
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@ -463,7 +463,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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//
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PointerPte = MiAddressToPte(Address);
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PointerPde = MiAddressToPde(Address);
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#if (_MI_PAGING_LEVELS >= 3)
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/* We need the PPE and PXE addresses */
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ASSERT(FALSE);
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#endif
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//
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// Check for dispatch-level snafu
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//
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@ -488,6 +492,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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//
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if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
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#if (_MI_PAGING_LEVELS >= 3)
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/* Need to check PXE and PDE validity */
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ASSERT(FALSE);
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#endif
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//
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// Is the PDE valid?
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//
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@ -497,12 +506,12 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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// Debug spew (eww!)
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//
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DPRINT("Invalid PDE\n");
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#if (_MI_PAGING_LEVELS == 2)
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//
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// Handle mapping in "Special" PDE directoreis
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//
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MiCheckPdeForPagedPool(Address);
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#endif
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//
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// Now we SHOULD be good
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//
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@ -556,7 +565,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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// This might happen...not sure yet
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//
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DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address, *PointerPte, *PointerPde);
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#if (_MI_PAGING_LEVELS == 2)
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//
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// Map in the page table
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//
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@ -565,7 +574,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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DPRINT1("PAGE TABLES FAULTED IN!\n");
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return STATUS_SUCCESS;
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}
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#endif
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//
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// Otherwise the page table doesn't actually exist
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//
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@ -650,6 +659,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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/* Lock the working set */
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MiLockProcessWorkingSet(CurrentProcess, CurrentThread);
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#if (_MI_PAGING_LEVELS >= 3)
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/* Need to check/handle PPE and PXE validity too */
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ASSERT(FALSE);
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#endif
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/* First things first, is the PDE valid? */
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ASSERT(PointerPde != MiAddressToPde(PTE_BASE));
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ASSERT(PointerPde->u.Hard.LargePage == 0);
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@ -679,6 +693,10 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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/* We should come back with APCs enabled, and with a valid PDE */
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ASSERT(KeAreAllApcsDisabled() == TRUE);
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#if (_MI_PAGING_LEVELS >= 3)
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/* Need to check/handle PPE and PXE validity too */
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ASSERT(FALSE);
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#endif
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ASSERT(PointerPde->u.Hard.Valid == 1);
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}
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@ -329,14 +329,16 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
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/* Request a page */
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PageFrameNumber = MiRemoveAnyPage(0);
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TempPte.u.Hard.PageFrameNumber = PageFrameNumber;
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#if (_MI_PAGING_LEVELS >= 3)
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/* On PAE/x64 systems, there's no double-buffering */
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ASSERT(FALSE);
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#else
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//
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// Save it into our double-buffered system page directory
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//
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#ifndef _M_AMD64
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/* This seems to be making the assumption that one PDE is one page long */
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C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
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#endif
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MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) /
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sizeof(MMPTE)] = TempPte;
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@ -347,7 +349,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
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/* Write the actual PTE now */
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MI_WRITE_VALID_PTE(PointerPte++, TempPte);
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#endif
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//
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// Move on to the next expansion address
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//
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