From a9fb81cbaefad623ffcb70305b4fbb608f6ca9b6 Mon Sep 17 00:00:00 2001 From: Sir Richard Date: Mon, 26 Jul 2010 21:45:42 +0000 Subject: [PATCH] [NTOS]: Another long-lost-promised straggler for Timo. There may be more of these needed, this is what I had done on my disk. svn path=/trunk/; revision=48288 --- reactos/ntoskrnl/mm/ARM3/mdlsup.c | 4 ++++ reactos/ntoskrnl/mm/ARM3/mminit.c | 31 +++++++++++++++++++++++++---- reactos/ntoskrnl/mm/ARM3/pagfault.c | 28 +++++++++++++++++++++----- reactos/ntoskrnl/mm/ARM3/pool.c | 10 ++++++---- 4 files changed, 60 insertions(+), 13 deletions(-) diff --git a/reactos/ntoskrnl/mm/ARM3/mdlsup.c b/reactos/ntoskrnl/mm/ARM3/mdlsup.c index 7363158605f..aa0d1f96b4d 100644 --- a/reactos/ntoskrnl/mm/ARM3/mdlsup.c +++ b/reactos/ntoskrnl/mm/ARM3/mdlsup.c @@ -813,6 +813,10 @@ MmProbeAndLockPages(IN PMDL Mdl, // Assume failure and check for non-mapped pages // *MdlPages = -1; +#if (_MI_PAGING_LEVELS >= 3) + /* Should be checking the PPE and PXE */ + ASSERT(FALSE); +#endif while ((PointerPde->u.Hard.Valid == 0) || (PointerPte->u.Hard.Valid == 0)) { diff --git a/reactos/ntoskrnl/mm/ARM3/mminit.c b/reactos/ntoskrnl/mm/ARM3/mminit.c index 28358f1b53e..ff34e733805 100644 --- a/reactos/ntoskrnl/mm/ARM3/mminit.c +++ b/reactos/ntoskrnl/mm/ARM3/mminit.c @@ -153,6 +153,7 @@ PMMPTE MiSessionLastPte; PVOID MiSystemViewStart; SIZE_T MmSystemViewSize; +#if (_MI_PAGING_LEVELS == 2) // // A copy of the system page directory (the page directory associated with the // System process) is kept (double-mapped) by the manager in order to lazily @@ -161,6 +162,7 @@ SIZE_T MmSystemViewSize; // PFN_NUMBER MmSystemPageDirectory[PD_COUNT]; PMMPTE MmSystemPagePtes; +#endif // // The system cache starts right after hyperspace. The first few pages are for @@ -228,6 +230,9 @@ PVOID MmSystemRangeStart; /* And these store the respective highest PTE/PDE address */ PMMPTE MiHighestUserPte; PMMPDE MiHighestUserPde; +#if (_MI_PAGING_LEVELS >= 3) +/* We need the highest PPE and PXE addresses */ +#endif /* These variables define the system cache address space */ PVOID MmSystemCacheStart; @@ -1476,7 +1481,7 @@ MiBuildPagedPool(VOID) PFN_NUMBER PageFrameIndex; KIRQL OldIrql; ULONG Size, BitMapSize; - +#if (_MI_PAGING_LEVELS == 2) // // Get the page frame number for the system page directory // @@ -1502,7 +1507,7 @@ MiBuildPagedPool(VOID) ASSERT(PD_COUNT == 1); TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0]; MI_WRITE_VALID_PTE(PointerPte, TempPte); - +#endif // // Let's get back to paged pool work: size it up. // By default, it should be twice as big as nonpaged pool. @@ -1554,6 +1559,14 @@ MiBuildPagedPool(VOID) // So now get the PDE for paged pool and zero it out // PointerPde = MiAddressToPde(MmPagedPoolStart); + +#if (_MI_PAGING_LEVELS >= 3) + /* On these systems, there's no double-mapping, so instead, the PPE and PXEs + * are setup to span the entire paged pool area, so there's no need for the + * system PD */ + ASSERT(FALSE); +#endif + RtlZeroMemory(PointerPde, (1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE)); @@ -1573,7 +1586,14 @@ MiBuildPagedPool(VOID) PageFrameIndex = MiRemoveZeroPage(0); TempPte.u.Hard.PageFrameNumber = PageFrameIndex; MI_WRITE_VALID_PTE(PointerPde, TempPte); - +#if (_MI_PAGING_LEVELS >= 3) + /* Use the PPE of MmPagedPoolStart that was setup above */ +// Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...)); + ASSERT(FALSE); +#else + /* Do it this way */ +// Bla = MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT] +#endif /* Initialize the PFN entry for it */ MiInitializePfnForOtherProcess(PageFrameIndex, PointerPde, @@ -1700,7 +1720,10 @@ MmArmInitSystem(IN ULONG Phase, /* Highest PTE and PDE based on the addresses above */ MiHighestUserPte = MiAddressToPte(MmHighestUserAddress); MiHighestUserPde = MiAddressToPde(MmHighestUserAddress); - +#if (_MI_PAGING_LEVELS >= 3) + /* We need the highest PPE and PXE addresses */ + ASSERT(FALSE); +#endif // // Get the size of the boot loader's image allocations and then round // that region up to a PDE size, so that any PDEs we might create for diff --git a/reactos/ntoskrnl/mm/ARM3/pagfault.c b/reactos/ntoskrnl/mm/ARM3/pagfault.c index ac56738feb0..9b1de7b7702 100644 --- a/reactos/ntoskrnl/mm/ARM3/pagfault.c +++ b/reactos/ntoskrnl/mm/ARM3/pagfault.c @@ -463,7 +463,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, // PointerPte = MiAddressToPte(Address); PointerPde = MiAddressToPde(Address); - +#if (_MI_PAGING_LEVELS >= 3) + /* We need the PPE and PXE addresses */ + ASSERT(FALSE); +#endif + // // Check for dispatch-level snafu // @@ -488,6 +492,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, // if (Mode == UserMode) return STATUS_ACCESS_VIOLATION; +#if (_MI_PAGING_LEVELS >= 3) + /* Need to check PXE and PDE validity */ + ASSERT(FALSE); +#endif + // // Is the PDE valid? // @@ -497,12 +506,12 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, // Debug spew (eww!) // DPRINT("Invalid PDE\n"); - +#if (_MI_PAGING_LEVELS == 2) // // Handle mapping in "Special" PDE directoreis // MiCheckPdeForPagedPool(Address); - +#endif // // Now we SHOULD be good // @@ -556,7 +565,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, // This might happen...not sure yet // DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address, *PointerPte, *PointerPde); - +#if (_MI_PAGING_LEVELS == 2) // // Map in the page table // @@ -565,7 +574,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, DPRINT1("PAGE TABLES FAULTED IN!\n"); return STATUS_SUCCESS; } - +#endif // // Otherwise the page table doesn't actually exist // @@ -650,6 +659,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, /* Lock the working set */ MiLockProcessWorkingSet(CurrentProcess, CurrentThread); +#if (_MI_PAGING_LEVELS >= 3) + /* Need to check/handle PPE and PXE validity too */ + ASSERT(FALSE); +#endif + /* First things first, is the PDE valid? */ ASSERT(PointerPde != MiAddressToPde(PTE_BASE)); ASSERT(PointerPde->u.Hard.LargePage == 0); @@ -679,6 +693,10 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, /* We should come back with APCs enabled, and with a valid PDE */ ASSERT(KeAreAllApcsDisabled() == TRUE); +#if (_MI_PAGING_LEVELS >= 3) + /* Need to check/handle PPE and PXE validity too */ + ASSERT(FALSE); +#endif ASSERT(PointerPde->u.Hard.Valid == 1); } diff --git a/reactos/ntoskrnl/mm/ARM3/pool.c b/reactos/ntoskrnl/mm/ARM3/pool.c index ab01fd1d7c4..57409b02ad1 100644 --- a/reactos/ntoskrnl/mm/ARM3/pool.c +++ b/reactos/ntoskrnl/mm/ARM3/pool.c @@ -329,14 +329,16 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, /* Request a page */ PageFrameNumber = MiRemoveAnyPage(0); TempPte.u.Hard.PageFrameNumber = PageFrameNumber; - + +#if (_MI_PAGING_LEVELS >= 3) + /* On PAE/x64 systems, there's no double-buffering */ + ASSERT(FALSE); +#else // // Save it into our double-buffered system page directory // -#ifndef _M_AMD64 /* This seems to be making the assumption that one PDE is one page long */ C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT))); -#endif MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) / sizeof(MMPTE)] = TempPte; @@ -347,7 +349,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, /* Write the actual PTE now */ MI_WRITE_VALID_PTE(PointerPte++, TempPte); - +#endif // // Move on to the next expansion address //