mirror of
https://github.com/reactos/reactos.git
synced 2024-10-08 02:13:56 +00:00
[NTOS]: Another long-lost-promised straggler for Timo. There may be more of these needed, this is what I had done on my disk.
svn path=/trunk/; revision=48288
This commit is contained in:
parent
91f37cae9a
commit
a9fb81cbae
|
@ -813,6 +813,10 @@ MmProbeAndLockPages(IN PMDL Mdl,
|
||||||
// Assume failure and check for non-mapped pages
|
// Assume failure and check for non-mapped pages
|
||||||
//
|
//
|
||||||
*MdlPages = -1;
|
*MdlPages = -1;
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* Should be checking the PPE and PXE */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
while ((PointerPde->u.Hard.Valid == 0) ||
|
while ((PointerPde->u.Hard.Valid == 0) ||
|
||||||
(PointerPte->u.Hard.Valid == 0))
|
(PointerPte->u.Hard.Valid == 0))
|
||||||
{
|
{
|
||||||
|
|
|
@ -153,6 +153,7 @@ PMMPTE MiSessionLastPte;
|
||||||
PVOID MiSystemViewStart;
|
PVOID MiSystemViewStart;
|
||||||
SIZE_T MmSystemViewSize;
|
SIZE_T MmSystemViewSize;
|
||||||
|
|
||||||
|
#if (_MI_PAGING_LEVELS == 2)
|
||||||
//
|
//
|
||||||
// A copy of the system page directory (the page directory associated with the
|
// A copy of the system page directory (the page directory associated with the
|
||||||
// System process) is kept (double-mapped) by the manager in order to lazily
|
// System process) is kept (double-mapped) by the manager in order to lazily
|
||||||
|
@ -161,6 +162,7 @@ SIZE_T MmSystemViewSize;
|
||||||
//
|
//
|
||||||
PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
|
PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
|
||||||
PMMPTE MmSystemPagePtes;
|
PMMPTE MmSystemPagePtes;
|
||||||
|
#endif
|
||||||
|
|
||||||
//
|
//
|
||||||
// The system cache starts right after hyperspace. The first few pages are for
|
// The system cache starts right after hyperspace. The first few pages are for
|
||||||
|
@ -228,6 +230,9 @@ PVOID MmSystemRangeStart;
|
||||||
/* And these store the respective highest PTE/PDE address */
|
/* And these store the respective highest PTE/PDE address */
|
||||||
PMMPTE MiHighestUserPte;
|
PMMPTE MiHighestUserPte;
|
||||||
PMMPDE MiHighestUserPde;
|
PMMPDE MiHighestUserPde;
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* We need the highest PPE and PXE addresses */
|
||||||
|
#endif
|
||||||
|
|
||||||
/* These variables define the system cache address space */
|
/* These variables define the system cache address space */
|
||||||
PVOID MmSystemCacheStart;
|
PVOID MmSystemCacheStart;
|
||||||
|
@ -1476,7 +1481,7 @@ MiBuildPagedPool(VOID)
|
||||||
PFN_NUMBER PageFrameIndex;
|
PFN_NUMBER PageFrameIndex;
|
||||||
KIRQL OldIrql;
|
KIRQL OldIrql;
|
||||||
ULONG Size, BitMapSize;
|
ULONG Size, BitMapSize;
|
||||||
|
#if (_MI_PAGING_LEVELS == 2)
|
||||||
//
|
//
|
||||||
// Get the page frame number for the system page directory
|
// Get the page frame number for the system page directory
|
||||||
//
|
//
|
||||||
|
@ -1502,7 +1507,7 @@ MiBuildPagedPool(VOID)
|
||||||
ASSERT(PD_COUNT == 1);
|
ASSERT(PD_COUNT == 1);
|
||||||
TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0];
|
TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0];
|
||||||
MI_WRITE_VALID_PTE(PointerPte, TempPte);
|
MI_WRITE_VALID_PTE(PointerPte, TempPte);
|
||||||
|
#endif
|
||||||
//
|
//
|
||||||
// Let's get back to paged pool work: size it up.
|
// Let's get back to paged pool work: size it up.
|
||||||
// By default, it should be twice as big as nonpaged pool.
|
// By default, it should be twice as big as nonpaged pool.
|
||||||
|
@ -1554,6 +1559,14 @@ MiBuildPagedPool(VOID)
|
||||||
// So now get the PDE for paged pool and zero it out
|
// So now get the PDE for paged pool and zero it out
|
||||||
//
|
//
|
||||||
PointerPde = MiAddressToPde(MmPagedPoolStart);
|
PointerPde = MiAddressToPde(MmPagedPoolStart);
|
||||||
|
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* On these systems, there's no double-mapping, so instead, the PPE and PXEs
|
||||||
|
* are setup to span the entire paged pool area, so there's no need for the
|
||||||
|
* system PD */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
|
|
||||||
RtlZeroMemory(PointerPde,
|
RtlZeroMemory(PointerPde,
|
||||||
(1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE));
|
(1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE));
|
||||||
|
|
||||||
|
@ -1573,7 +1586,14 @@ MiBuildPagedPool(VOID)
|
||||||
PageFrameIndex = MiRemoveZeroPage(0);
|
PageFrameIndex = MiRemoveZeroPage(0);
|
||||||
TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
|
TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
|
||||||
MI_WRITE_VALID_PTE(PointerPde, TempPte);
|
MI_WRITE_VALID_PTE(PointerPde, TempPte);
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* Use the PPE of MmPagedPoolStart that was setup above */
|
||||||
|
// Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...));
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#else
|
||||||
|
/* Do it this way */
|
||||||
|
// Bla = MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT]
|
||||||
|
#endif
|
||||||
/* Initialize the PFN entry for it */
|
/* Initialize the PFN entry for it */
|
||||||
MiInitializePfnForOtherProcess(PageFrameIndex,
|
MiInitializePfnForOtherProcess(PageFrameIndex,
|
||||||
PointerPde,
|
PointerPde,
|
||||||
|
@ -1700,7 +1720,10 @@ MmArmInitSystem(IN ULONG Phase,
|
||||||
/* Highest PTE and PDE based on the addresses above */
|
/* Highest PTE and PDE based on the addresses above */
|
||||||
MiHighestUserPte = MiAddressToPte(MmHighestUserAddress);
|
MiHighestUserPte = MiAddressToPte(MmHighestUserAddress);
|
||||||
MiHighestUserPde = MiAddressToPde(MmHighestUserAddress);
|
MiHighestUserPde = MiAddressToPde(MmHighestUserAddress);
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* We need the highest PPE and PXE addresses */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
//
|
//
|
||||||
// Get the size of the boot loader's image allocations and then round
|
// Get the size of the boot loader's image allocations and then round
|
||||||
// that region up to a PDE size, so that any PDEs we might create for
|
// that region up to a PDE size, so that any PDEs we might create for
|
||||||
|
|
|
@ -463,6 +463,10 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
//
|
//
|
||||||
PointerPte = MiAddressToPte(Address);
|
PointerPte = MiAddressToPte(Address);
|
||||||
PointerPde = MiAddressToPde(Address);
|
PointerPde = MiAddressToPde(Address);
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* We need the PPE and PXE addresses */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
|
|
||||||
//
|
//
|
||||||
// Check for dispatch-level snafu
|
// Check for dispatch-level snafu
|
||||||
|
@ -488,6 +492,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
//
|
//
|
||||||
if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
|
if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
|
||||||
|
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* Need to check PXE and PDE validity */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
|
|
||||||
//
|
//
|
||||||
// Is the PDE valid?
|
// Is the PDE valid?
|
||||||
//
|
//
|
||||||
|
@ -497,12 +506,12 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
// Debug spew (eww!)
|
// Debug spew (eww!)
|
||||||
//
|
//
|
||||||
DPRINT("Invalid PDE\n");
|
DPRINT("Invalid PDE\n");
|
||||||
|
#if (_MI_PAGING_LEVELS == 2)
|
||||||
//
|
//
|
||||||
// Handle mapping in "Special" PDE directoreis
|
// Handle mapping in "Special" PDE directoreis
|
||||||
//
|
//
|
||||||
MiCheckPdeForPagedPool(Address);
|
MiCheckPdeForPagedPool(Address);
|
||||||
|
#endif
|
||||||
//
|
//
|
||||||
// Now we SHOULD be good
|
// Now we SHOULD be good
|
||||||
//
|
//
|
||||||
|
@ -556,7 +565,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
// This might happen...not sure yet
|
// This might happen...not sure yet
|
||||||
//
|
//
|
||||||
DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address, *PointerPte, *PointerPde);
|
DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address, *PointerPte, *PointerPde);
|
||||||
|
#if (_MI_PAGING_LEVELS == 2)
|
||||||
//
|
//
|
||||||
// Map in the page table
|
// Map in the page table
|
||||||
//
|
//
|
||||||
|
@ -565,7 +574,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
DPRINT1("PAGE TABLES FAULTED IN!\n");
|
DPRINT1("PAGE TABLES FAULTED IN!\n");
|
||||||
return STATUS_SUCCESS;
|
return STATUS_SUCCESS;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
//
|
//
|
||||||
// Otherwise the page table doesn't actually exist
|
// Otherwise the page table doesn't actually exist
|
||||||
//
|
//
|
||||||
|
@ -650,6 +659,11 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
/* Lock the working set */
|
/* Lock the working set */
|
||||||
MiLockProcessWorkingSet(CurrentProcess, CurrentThread);
|
MiLockProcessWorkingSet(CurrentProcess, CurrentThread);
|
||||||
|
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* Need to check/handle PPE and PXE validity too */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
|
|
||||||
/* First things first, is the PDE valid? */
|
/* First things first, is the PDE valid? */
|
||||||
ASSERT(PointerPde != MiAddressToPde(PTE_BASE));
|
ASSERT(PointerPde != MiAddressToPde(PTE_BASE));
|
||||||
ASSERT(PointerPde->u.Hard.LargePage == 0);
|
ASSERT(PointerPde->u.Hard.LargePage == 0);
|
||||||
|
@ -679,6 +693,10 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
|
||||||
|
|
||||||
/* We should come back with APCs enabled, and with a valid PDE */
|
/* We should come back with APCs enabled, and with a valid PDE */
|
||||||
ASSERT(KeAreAllApcsDisabled() == TRUE);
|
ASSERT(KeAreAllApcsDisabled() == TRUE);
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* Need to check/handle PPE and PXE validity too */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#endif
|
||||||
ASSERT(PointerPde->u.Hard.Valid == 1);
|
ASSERT(PointerPde->u.Hard.Valid == 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -330,13 +330,15 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
|
||||||
PageFrameNumber = MiRemoveAnyPage(0);
|
PageFrameNumber = MiRemoveAnyPage(0);
|
||||||
TempPte.u.Hard.PageFrameNumber = PageFrameNumber;
|
TempPte.u.Hard.PageFrameNumber = PageFrameNumber;
|
||||||
|
|
||||||
|
#if (_MI_PAGING_LEVELS >= 3)
|
||||||
|
/* On PAE/x64 systems, there's no double-buffering */
|
||||||
|
ASSERT(FALSE);
|
||||||
|
#else
|
||||||
//
|
//
|
||||||
// Save it into our double-buffered system page directory
|
// Save it into our double-buffered system page directory
|
||||||
//
|
//
|
||||||
#ifndef _M_AMD64
|
|
||||||
/* This seems to be making the assumption that one PDE is one page long */
|
/* This seems to be making the assumption that one PDE is one page long */
|
||||||
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
|
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
|
||||||
#endif
|
|
||||||
MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) /
|
MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) /
|
||||||
sizeof(MMPTE)] = TempPte;
|
sizeof(MMPTE)] = TempPte;
|
||||||
|
|
||||||
|
@ -347,7 +349,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
|
||||||
|
|
||||||
/* Write the actual PTE now */
|
/* Write the actual PTE now */
|
||||||
MI_WRITE_VALID_PTE(PointerPte++, TempPte);
|
MI_WRITE_VALID_PTE(PointerPte++, TempPte);
|
||||||
|
#endif
|
||||||
//
|
//
|
||||||
// Move on to the next expansion address
|
// Move on to the next expansion address
|
||||||
//
|
//
|
||||||
|
|
Loading…
Reference in a new issue