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- Documentative amendment to 44115: It incorrectly stated that the commit added "init(i)al support for PCI and ISA interrupts". What was added is (disabled) initial support for ISA, EISA and PCI configurations that require level-triggered interrupts (we only support edge-triggered interrupts right now) and PCI IRQ routing, along with proper handling of IRQ13.
svn path=/trunk/; revision=44121
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1 changed files with 2 additions and 2 deletions
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@ -20,7 +20,7 @@ PICInitTable:
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/* Master PIC */
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/* Master PIC */
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.short 0x20 /* Port */
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.short 0x20 /* Port */
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.byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */
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.byte 0x11 /* Edge, cascade, CAI 8, ICW4 */
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.byte PRIMARY_VECTOR_BASE /* Base */
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.byte PRIMARY_VECTOR_BASE /* Base */
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.byte 4 /* IRQ 4 connected to slave */
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.byte 4 /* IRQ 4 connected to slave */
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.byte 1 /* Non buffered, not nested, 8086 */
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.byte 1 /* Non buffered, not nested, 8086 */
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@ -798,7 +798,7 @@ _KeRaiseIrqlToDpcLevel@0:
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mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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#if DBG
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#if DBG
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/* Make sure we were not higher then dispatch */
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/* Make sure we were not higher then synch */
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cmp eax, DISPATCH_LEVEL
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cmp eax, DISPATCH_LEVEL
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ja InvalidRaise
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ja InvalidRaise
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#endif
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#endif
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