From a8286c3821d89004945ee3bd281470092994fda0 Mon Sep 17 00:00:00 2001 From: Stefan Ginsberg Date: Thu, 12 Nov 2009 21:46:52 +0000 Subject: [PATCH] - Documentative amendment to 44115: It incorrectly stated that the commit added "init(i)al support for PCI and ISA interrupts". What was added is (disabled) initial support for ISA, EISA and PCI configurations that require level-triggered interrupts (we only support edge-triggered interrupts right now) and PCI IRQ routing, along with proper handling of IRQ13. svn path=/trunk/; revision=44121 --- reactos/hal/halx86/generic/irq.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/reactos/hal/halx86/generic/irq.S b/reactos/hal/halx86/generic/irq.S index ae78a4b86e7..2b4e70f1062 100644 --- a/reactos/hal/halx86/generic/irq.S +++ b/reactos/hal/halx86/generic/irq.S @@ -20,7 +20,7 @@ PICInitTable: /* Master PIC */ .short 0x20 /* Port */ - .byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */ + .byte 0x11 /* Edge, cascade, CAI 8, ICW4 */ .byte PRIMARY_VECTOR_BASE /* Base */ .byte 4 /* IRQ 4 connected to slave */ .byte 1 /* Non buffered, not nested, 8086 */ @@ -798,7 +798,7 @@ _KeRaiseIrqlToDpcLevel@0: mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL #if DBG - /* Make sure we were not higher then dispatch */ + /* Make sure we were not higher then synch */ cmp eax, DISPATCH_LEVEL ja InvalidRaise #endif