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- Documentative amendment to 44115: It incorrectly stated that the commit added "init(i)al support for PCI and ISA interrupts". What was added is (disabled) initial support for ISA, EISA and PCI configurations that require level-triggered interrupts (we only support edge-triggered interrupts right now) and PCI IRQ routing, along with proper handling of IRQ13.

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svn path=/trunk/; revision=44121
This commit is contained in:
Stefan Ginsberg 2009-11-12 21:46:52 +00:00
parent 69b02e1155
commit a8286c3821
1 changed files with 2 additions and 2 deletions
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4
reactos/hal/halx86/generic/irq.S
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@ -20,7 +20,7 @@ PICInitTable:
/* Master PIC */
.short 0x20 /* Port */
.byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */
.byte 0x11 /* Edge, cascade, CAI 8, ICW4 */
.byte PRIMARY_VECTOR_BASE /* Base */
.byte 4 /* IRQ 4 connected to slave */
.byte 1 /* Non buffered, not nested, 8086 */
@ -798,7 +798,7 @@ _KeRaiseIrqlToDpcLevel@0:
mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
#if DBG
/* Make sure we were not higher then dispatch */
/* Make sure we were not higher then synch */
cmp eax, DISPATCH_LEVEL
ja InvalidRaise
#endif