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[NTOS]: Fix 16-bit interlocked operations on ARM (GCC doesn't provide built-ins). ARM should build now.
svn path=/trunk/; revision=49782
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@ -67,12 +67,40 @@ __INTRIN_INLINE char _InterlockedCompareExchange8(volatile char * const Destinat
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__INTRIN_INLINE short _InterlockedCompareExchange16(volatile short * const Destination, const short Exchange, const short Comperand)
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__INTRIN_INLINE short _InterlockedCompareExchange16(volatile short * const Destination, const short Exchange, const short Comperand)
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{
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{
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return __sync_val_compare_and_swap(Destination, Comperand, Exchange);
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short a, b;
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__asm__ __volatile__ ( "0:\n\t"
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"ldr %1, [%2]\n\t"
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"cmp %1, %4\n\t"
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"bne 1f\n\t"
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"swp %0, %3, [%2]\n\t"
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"cmp %0, %1\n\t"
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"swpne %3, %0, [%2]\n\t"
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"bne 0b\n\t"
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"1:"
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: "=&r" (a), "=&r" (b)
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: "r" (Destination), "r" (Exchange), "r" (Comperand)
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: "cc", "memory");
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return a;
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}
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}
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__INTRIN_INLINE long _InterlockedExchangeAdd16(volatile short * const Addend, const short Value)
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__INTRIN_INLINE short _InterlockedExchangeAdd16(volatile short * const Addend, const short Value)
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{
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{
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return __sync_fetch_and_add(Addend, Value);
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short a, b, c;
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__asm__ __volatile__ ( "0:\n\t"
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"ldr %0, [%3]\n\t"
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"add %1, %0, %4\n\t"
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"swp %2, %1, [%3]\n\t"
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"cmp %0, %2\n\t"
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"swpne %1, %2, [%3]\n\t"
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"bne 0b"
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: "=&r" (a), "=&r" (b), "=&r" (c)
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: "r" (Value), "r" (Addend)
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: "cc", "memory");
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return a;
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}
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}
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__INTRIN_INLINE long _InterlockedCompareExchange(volatile long * const dest, const long exch, const long comp)
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__INTRIN_INLINE long _InterlockedCompareExchange(volatile long * const dest, const long exch, const long comp)
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