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[NTOSKRNL]
- implement helper functions MiIsMemoryTypeFree and MiIsMemoryTypeInvisible - use symbolic names instead of hex values - Don't ASSERT on mising large page support, just warn - add some more mm macros for amd64 svn path=/trunk/; revision=53902
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4 changed files with 59 additions and 13 deletions
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@ -93,6 +93,9 @@
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/* Easy accessing PFN in PTE */
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
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// FIXME, only copied from x86
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// FIXME, only copied from x86
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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@ -192,15 +195,35 @@ MiAddressToPxi(PVOID Address)
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/* Convert a PTE into a corresponding address */
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/* Convert a PTE into a corresponding address */
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PVOID
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PVOID
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FORCEINLINE
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FORCEINLINE
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MiPteToAddress(PMMPTE Pte)
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MiPteToAddress(PMMPTE PointerPte)
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{
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{
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/* Use signed math */
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/* Use signed math */
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LONG64 Temp = (LONG64)Pte;
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return (PVOID)(((LONG64)PointerPte << 25) >> 16);
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Temp <<= 25;
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}
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Temp >>= 16;
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return (PVOID)Temp;
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PVOID
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FORCEINLINE
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MiPdeToAddress(PMMPTE PointerPde)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPde << 34) >> 16);
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}
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PVOID
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FORCEINLINE
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MiPpeToAddress(PMMPTE PointerPpe)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
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}
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PVOID
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FORCEINLINE
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MiPxeToAddress(PMMPTE PointerPxe)
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{
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/* Use signed math */
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return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
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}
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}
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#define MiPdeToAddress MiPteToAddress
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BOOLEAN
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BOOLEAN
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FORCEINLINE
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FORCEINLINE
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@ -34,8 +34,8 @@ INIT_FUNCTION
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MiInitializeLargePageSupport(VOID)
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MiInitializeLargePageSupport(VOID)
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{
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{
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#if _MI_PAGING_LEVELS > 2
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#if _MI_PAGING_LEVELS > 2
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DPRINT1("PAE/x64 Not Implemented\n");
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DPRINT1("MiInitializeLargePageSupport: PAE/x64 Not Implemented\n");
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ASSERT(FALSE);
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//ASSERT(FALSE);
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#else
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#else
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/* Initialize the large-page hyperspace PTE used for initial mapping */
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/* Initialize the large-page hyperspace PTE used for initial mapping */
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MiLargePageHyperPte = MiReserveSystemPtes(1, SystemPteSpace);
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MiLargePageHyperPte = MiReserveSystemPtes(1, SystemPteSpace);
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@ -538,6 +538,27 @@ extern PVOID MiSessionPoolEnd; // 0xBE000000
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extern PVOID MiSessionPoolStart; // 0xBD000000
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extern PVOID MiSessionPoolStart; // 0xBD000000
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extern PVOID MiSessionViewStart; // 0xBE000000
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extern PVOID MiSessionViewStart; // 0xBE000000
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BOOLEAN
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FORCEINLINE
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MiIsMemoryTypeFree(TYPE_OF_MEMORY MemoryType)
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{
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return ((MemoryType == LoaderFree) ||
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(MemoryType == LoaderLoadedProgram) ||
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(MemoryType == LoaderFirmwareTemporary) ||
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(MemoryType == LoaderOsloaderStack));
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}
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BOOLEAN
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FORCEINLINE
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MiIsMemoryTypeInvisible(TYPE_OF_MEMORY MemoryType)
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{
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return ((MemoryType == LoaderFirmwarePermanent) ||
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(MemoryType == LoaderSpecialMemory) ||
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(MemoryType == LoaderHALCachedMemory) ||
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(MemoryType == LoaderBBTMemory));
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}
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//
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//
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// Figures out the hardware bits for a PTE
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// Figures out the hardware bits for a PTE
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//
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//
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@ -572,15 +572,16 @@ MiInitializeColorTables(VOID)
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for (i = 0; i < MmSecondaryColors; i++)
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for (i = 0; i < MmSecondaryColors; i++)
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{
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{
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/* Set both free and zero lists for each color */
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/* Set both free and zero lists for each color */
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MmFreePagesByColor[ZeroedPageList][i].Flink = 0xFFFFFFFF;
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MmFreePagesByColor[ZeroedPageList][i].Flink = LIST_HEAD;
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MmFreePagesByColor[ZeroedPageList][i].Blink = (PVOID)0xFFFFFFFF;
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MmFreePagesByColor[ZeroedPageList][i].Blink = (PVOID)LIST_HEAD;
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MmFreePagesByColor[ZeroedPageList][i].Count = 0;
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MmFreePagesByColor[ZeroedPageList][i].Count = 0;
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MmFreePagesByColor[FreePageList][i].Flink = 0xFFFFFFFF;
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MmFreePagesByColor[FreePageList][i].Flink = LIST_HEAD;
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MmFreePagesByColor[FreePageList][i].Blink = (PVOID)0xFFFFFFFF;
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MmFreePagesByColor[FreePageList][i].Blink = (PVOID)LIST_HEAD;
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MmFreePagesByColor[FreePageList][i].Count = 0;
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MmFreePagesByColor[FreePageList][i].Count = 0;
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}
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}
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}
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}
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#ifndef _M_AMD64
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BOOLEAN
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BOOLEAN
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NTAPI
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NTAPI
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INIT_FUNCTION
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INIT_FUNCTION
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@ -1059,6 +1060,7 @@ MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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/* Finally add the pages for the PFN database itself */
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/* Finally add the pages for the PFN database itself */
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MiBuildPfnDatabaseSelf();
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MiBuildPfnDatabaseSelf();
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}
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}
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#endif /* !_M_AMD64 */
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VOID
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VOID
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NTAPI
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NTAPI
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@ -1287,7 +1289,7 @@ MiAddHalIoMappings(VOID)
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PFN_NUMBER PageFrameIndex;
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PFN_NUMBER PageFrameIndex;
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/* HAL Heap address -- should be on a PDE boundary */
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/* HAL Heap address -- should be on a PDE boundary */
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BaseAddress = (PVOID)0xFFC00000;
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BaseAddress = (PVOID)MM_HAL_VA_START;
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ASSERT(MiAddressToPteOffset(BaseAddress) == 0);
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ASSERT(MiAddressToPteOffset(BaseAddress) == 0);
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/* Check how many PDEs the heap has */
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/* Check how many PDEs the heap has */
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