diff --git a/reactos/ntoskrnl/include/internal/amd64/mm.h b/reactos/ntoskrnl/include/internal/amd64/mm.h
index b5ae54a9399..946208dc69c 100644
--- a/reactos/ntoskrnl/include/internal/amd64/mm.h
+++ b/reactos/ntoskrnl/include/internal/amd64/mm.h
@@ -93,6 +93,9 @@
 
 /* Easy accessing PFN in PTE */
 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
+#define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
+#define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
+#define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
 
 // FIXME, only copied from x86
 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
@@ -192,15 +195,35 @@ MiAddressToPxi(PVOID Address)
 /* Convert a PTE into a corresponding address */
 PVOID
 FORCEINLINE
-MiPteToAddress(PMMPTE Pte)
+MiPteToAddress(PMMPTE PointerPte)
 {
     /* Use signed math */
-    LONG64 Temp = (LONG64)Pte;
-    Temp <<= 25;
-    Temp >>= 16;
-    return (PVOID)Temp;
+    return (PVOID)(((LONG64)PointerPte << 25) >> 16);
+}
+
+PVOID
+FORCEINLINE
+MiPdeToAddress(PMMPTE PointerPde)
+{
+    /* Use signed math */
+    return (PVOID)(((LONG64)PointerPde << 34) >> 16);
+}
+
+PVOID
+FORCEINLINE
+MiPpeToAddress(PMMPTE PointerPpe)
+{
+    /* Use signed math */
+    return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
+}
+
+PVOID
+FORCEINLINE
+MiPxeToAddress(PMMPTE PointerPxe)
+{
+    /* Use signed math */
+    return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
 }
-#define MiPdeToAddress MiPteToAddress
 
 BOOLEAN
 FORCEINLINE
diff --git a/reactos/ntoskrnl/mm/ARM3/largepag.c b/reactos/ntoskrnl/mm/ARM3/largepag.c
index b53f15a9b8d..49ce25fc71a 100644
--- a/reactos/ntoskrnl/mm/ARM3/largepag.c
+++ b/reactos/ntoskrnl/mm/ARM3/largepag.c
@@ -34,8 +34,8 @@ INIT_FUNCTION
 MiInitializeLargePageSupport(VOID)
 {
 #if _MI_PAGING_LEVELS > 2
-    DPRINT1("PAE/x64 Not Implemented\n");
-    ASSERT(FALSE);
+    DPRINT1("MiInitializeLargePageSupport: PAE/x64 Not Implemented\n");
+    //ASSERT(FALSE);
 #else
     /* Initialize the large-page hyperspace PTE used for initial mapping */
     MiLargePageHyperPte = MiReserveSystemPtes(1, SystemPteSpace);
diff --git a/reactos/ntoskrnl/mm/ARM3/miarm.h b/reactos/ntoskrnl/mm/ARM3/miarm.h
index eeb499de980..8cca84f104d 100644
--- a/reactos/ntoskrnl/mm/ARM3/miarm.h
+++ b/reactos/ntoskrnl/mm/ARM3/miarm.h
@@ -538,6 +538,27 @@ extern PVOID MiSessionPoolEnd;     // 0xBE000000
 extern PVOID MiSessionPoolStart;   // 0xBD000000
 extern PVOID MiSessionViewStart;   // 0xBE000000
 
+BOOLEAN
+FORCEINLINE
+MiIsMemoryTypeFree(TYPE_OF_MEMORY MemoryType)
+{
+    return ((MemoryType == LoaderFree) ||
+            (MemoryType == LoaderLoadedProgram) ||
+            (MemoryType == LoaderFirmwareTemporary) ||
+            (MemoryType == LoaderOsloaderStack));
+}
+
+BOOLEAN
+FORCEINLINE
+MiIsMemoryTypeInvisible(TYPE_OF_MEMORY MemoryType)
+{
+    return ((MemoryType == LoaderFirmwarePermanent) ||
+            (MemoryType == LoaderSpecialMemory) ||
+            (MemoryType == LoaderHALCachedMemory) ||
+            (MemoryType == LoaderBBTMemory));
+}
+
+
 //
 // Figures out the hardware bits for a PTE
 //
diff --git a/reactos/ntoskrnl/mm/ARM3/mminit.c b/reactos/ntoskrnl/mm/ARM3/mminit.c
index f5ca8c2d6cb..508713b3842 100644
--- a/reactos/ntoskrnl/mm/ARM3/mminit.c
+++ b/reactos/ntoskrnl/mm/ARM3/mminit.c
@@ -572,15 +572,16 @@ MiInitializeColorTables(VOID)
     for (i = 0; i < MmSecondaryColors; i++)
     {
         /* Set both free and zero lists for each color */
-        MmFreePagesByColor[ZeroedPageList][i].Flink = 0xFFFFFFFF;
-        MmFreePagesByColor[ZeroedPageList][i].Blink = (PVOID)0xFFFFFFFF;
+        MmFreePagesByColor[ZeroedPageList][i].Flink = LIST_HEAD;
+        MmFreePagesByColor[ZeroedPageList][i].Blink = (PVOID)LIST_HEAD;
         MmFreePagesByColor[ZeroedPageList][i].Count = 0;
-        MmFreePagesByColor[FreePageList][i].Flink = 0xFFFFFFFF;
-        MmFreePagesByColor[FreePageList][i].Blink = (PVOID)0xFFFFFFFF;
+        MmFreePagesByColor[FreePageList][i].Flink = LIST_HEAD;
+        MmFreePagesByColor[FreePageList][i].Blink = (PVOID)LIST_HEAD;
         MmFreePagesByColor[FreePageList][i].Count = 0;
     }
 }
 
+#ifndef _M_AMD64
 BOOLEAN
 NTAPI
 INIT_FUNCTION
@@ -1059,6 +1060,7 @@ MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
     /* Finally add the pages for the PFN database itself */
     MiBuildPfnDatabaseSelf();
 }
+#endif /* !_M_AMD64 */
 
 VOID
 NTAPI
@@ -1287,7 +1289,7 @@ MiAddHalIoMappings(VOID)
     PFN_NUMBER PageFrameIndex;
 
     /* HAL Heap address -- should be on a PDE boundary */
-    BaseAddress = (PVOID)0xFFC00000;
+    BaseAddress = (PVOID)MM_HAL_VA_START;
     ASSERT(MiAddressToPteOffset(BaseAddress) == 0);
 
     /* Check how many PDEs the heap has */