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[FREELDR/x64] Set up CR0/CR4 for SSE instructions

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Newer GCC starts emitting SSE/SSE2 instructions, which would cause a triple fault, during early boot, if not enabled.
This commit is contained in:
Timo Kreuzer 2024-03-11 23:31:58 +02:00
parent 8ba6c66890
commit 43fc73207d
2 changed files with 15 additions and 3 deletions
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13
boot/freeldr/freeldr/arch/amd64/entry.S
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@ -1,5 +1,6 @@
#include <asm.inc> #include <asm.inc>
#include <ksamd64.inc>
#include <arch/pc/x86common.h> #include <arch/pc/x86common.h>
#include <arch/pc/pcbios.h> #include <arch/pc/pcbios.h>
@ -38,6 +39,18 @@ ContinueAddress:
FrldrStartup: FrldrStartup:
/* Set up CR0 for SSE */
mov rax, cr0
and eax, not CR0_EM // Clear coprocessor emulation CR0.EM CR0.EM (bit 2)
or rax, CR0_MP // Set coprocessor monitoring CR0.MP (bit 1)
mov cr0, rax
/* Set up CR4 for SSE */
mov rax, cr4
or eax, CR4_FXSR // Enable fx save/restore CR4.OSFXSR (bit 9)
or eax, CR4_XMMEXCPT // Enable XMMI exceptions CR4.OSXMMEXCPT (bit 10)
mov cr4, rax
/* Store BootDrive and BootPartition */ /* Store BootDrive and BootPartition */
mov al, byte ptr [BSS_BootDrive] mov al, byte ptr [BSS_BootDrive]
mov byte ptr [FrldrBootDrive], al mov byte ptr [FrldrBootDrive], al

5
boot/freeldr/freeldr/arch/realmode/amd64.S
View file

@ -322,9 +322,8 @@ ExitToLongMode:
mov word ptr ds:[stack16], sp mov word ptr ds:[stack16], sp
/* Set PAE and PGE: 10100000b */ /* Set PAE and PGE: 10100000b */
// mov eax, cr4 mov eax, cr4
// or eax, HEX(00A0) or eax, HEX(00A0)
mov eax, HEX(00A0)
mov cr4, eax mov cr4, eax
/* Point cr3 at the PML4 */ /* Point cr3 at the PML4 */