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[CPORTLIB][NTOS:INBV][KDCOM][FREELDR] Add ComPort library for NEC PC-98 series (#2407)

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There are 2 known serial ports:
    COM1 - based on Intel 8251A
    COM2 - National Semiconductor 16550
This commit is contained in:
Dmitry Borisov 2020-03-07 00:50:31 +06:00 • committed by GitHub
parent a6515e2b75
commit 222e79232c
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GPG key ID: 4AEE18F83AFDEB23
12 changed files with 1104 additions and 1 deletions
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28
sdk/include/reactos/drivers/pc98/cpu.h Normal file
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/*
* PROJECT: NEC PC-98 series onboard hardware
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: CPU I/O ports header file
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
*/
#pragma once
#define CPU_IO_o_RESET 0x0F
#define CPU_IO_o_A20_UNMASK 0xF2
#define CPU_IO_o_A20_CONTROL 0xF6
#define CPU_A20_ENABLE 0x02
#define CPU_A20_DISABLE 0x03
/*
* ARTIC (A Relative Time Indication Counter) - 24-bit binary up counter
*/
#define CPU_IO_o_ARTIC_DELAY 0x5F /* Constant delay (about 600 ns) */
#define CPU_IO_i_ARTIC_0 0x5C
#define CPU_IO_i_ARTIC_1 0x5D
#define CPU_IO_i_ARTIC_2 0x5E
#define CPU_IO_i_ARTIC_3 0x5F
#define ARTIC_FREQUENCY 307200
#define ARTIC_FREQUENCY_0_1 ARTIC_FREQUENCY
#define ARTIC_FREQUENCY_2_3 (ARTIC_FREQUENCY >> 8)

97
sdk/include/reactos/drivers/pc98/pit.h Normal file
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/*
* PROJECT: NEC PC-98 series on-board hardware
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: Intel 8253A PIT header file
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
*/
#pragma once
#define TIMER_CHANNEL0_DATA_PORT 0x71
#define TIMER_CHANNEL1_DATA_PORT 0x73
#define TIMER_CHANNEL2_DATA_PORT 0x75
#define TIMER_CONTROL_PORT 0x77
/* Tick rate of PIT depends on system clock frequency */
#define TIMER_FREQUENCY_1 1996800 /* 8 MHz */
#define TIMER_FREQUENCY_2 2457600 /* 10 MHz, 5 MHz */
typedef enum _TIMER_OPERATING_MODES
{
/* Interrupt On Terminal Count */
PitOperatingMode0,
/* Hardware Re-triggerable One-Shot */
PitOperatingMode1,
/* Rate Generator */
PitOperatingMode2,
/* Square Wave Generator */
PitOperatingMode3,
/* Software Triggered Strobe */
PitOperatingMode4,
/* Hardware Triggered Strobe */
PitOperatingMode5
} TIMER_OPERATING_MODES;
typedef enum _TIMER_ACCESS_MODES
{
PitAccessModeCounterLatch,
PitAccessModeLow,
PitAccessModeHigh,
PitAccessModeLowHigh
} TIMER_ACCESS_MODES;
typedef enum _TIMER_CHANNELS
{
/* IRQ 0 */
PitChannel0,
/* PC Speaker */
PitChannel1,
/* RS-232 chipset */
PitChannel2,
/* Execute multiple latch command */
MultipleLatch
} TIMER_CHANNELS;
typedef union _TIMER_CONTROL_PORT_REGISTER
{
struct
{
UCHAR BcdMode:1;
UCHAR OperatingMode:3;
UCHAR AccessMode:2;
UCHAR Channel:2;
};
UCHAR Bits;
} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
FORCEINLINE
ULONG
Read8253Timer(TIMER_CHANNELS TimerChannel)
{
ULONG Count;
WRITE_PORT_UCHAR((PUCHAR)TIMER_CONTROL_PORT, (TimerChannel << 6) | PitAccessModeCounterLatch);
Count = READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2));
Count |= READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2)) << 8;
return Count;
}
FORCEINLINE
VOID
Write8253Timer(
TIMER_CONTROL_PORT_REGISTER TimerControl,
USHORT Count)
{
WRITE_PORT_UCHAR((PUCHAR)TIMER_CONTROL_PORT, TimerControl.Bits);
WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), Count & 0xFF);
WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), (Count >> 8) & 0xFF);
}

184
sdk/include/reactos/drivers/pc98/serial.h Normal file
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/*
* PROJECT: NEC PC-98 series onboard hardware
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: UART header file
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
*/
#pragma once
/* COM1 (Intel 8251A-based UART) **********************************************/
/*
* UART registers and definitions
*/
#define SER1_IO_i_DATA 0x030
#define SER1_IO_i_STATUS 0x032
#define SER1_STATUS_TxRDY 0x01 /* Transmitter ready */
#define SER1_STATUS_RxRDY 0x02 /* Receiver ready */
#define SER1_STATUS_TxEMPTY 0x04 /* Transmitter empty */
#define SER1_STATUS_PE 0x08 /* Parity error */
#define SER1_STATUS_OE 0x10 /* Overrun error */
#define SER1_STATUS_FE 0x20 /* Framing error */
#define SER1_STATUS_SYNDET 0x40 /* Sync detect / Break detect */
#define SER1_STATUS_DSR 0x80 /* Data set ready */
#define SER1_IO_i_RECEIVER_BUFFER 0x130
#define SER1_IO_i_LINE_STATUS 0x132
#define SER1_LSR_TxEMPTY 0x01 /* Transmitter empty */
#define SER1_LSR_TxRDY 0x02 /* Transmitter ready */
#define SER1_LSR_RxRDY 0x04 /* Receiver ready */
#define SER1_LSR_OE 0x10 /* Overrun error */
#define SER1_LSR_PE 0x20 /* Parity error */
#define SER1_LSR_BI 0x80 /* Break detect */
#define SER1_IO_i_MODEM_STATUS 0x134
#define SER_MSR_CTS_CHANGED 0x01 /* Change in clear to send */
#define SER_MSR_DSR_CHANGED 0x02 /* Change in data set ready */
#define SER_MSR_RI_CHANGED 0x04 /* Trailing edge ring indicator */
#define SER_MSR_DCD_CHANGED 0x08 /* Change in carrier detect */
#define SER_MSR_CTS 0x10 /* Clear to send */
#define SER_MSR_DSR 0x20 /* Data set ready */
#define SER_MSR_RI 0x40 /* Ring indicator */
#define SER_MSR_DCD 0x80 /* Data carrier detect */
#define SER1_IO_i_INTERRUPT_ID 0x136
#define SER_IIR_MS 0x00 /* Modem status change */
#define SER_IIR_THR 0x02 /* Transmitter holding register empty */
#define SER_IIR_RDA 0x04 /* Received data acailable */
#define SER_IIR_RLS 0x06 /* Receiver line status change */
#define SER_IIR_CTI 0x0C /* Character timeout */
#define SER_IIR_ID_MASK 0x0F
#define SER_IIR_SELF 0x01 /* No interrupt pending */
#define SER1_IIR_MUST_BE_ZERO 0x20
#define SER1_IIR_FIFOS_ENABLED 0x40 /* Toggles for each read */
#define SER1_IO_i_FIFO_CONTROL 0x138
#define SER1_IO_i_DIVISOR_LATCH 0x13A
#define SER1_IO_o_DATA 0x030
#define SER1_IO_o_MODE_COMMAND 0x032
/* Parity generate/check */
#define SER1_MODE_PEN 0x10 /* Parity enable */
#define SER1_MODE_EP 0x20 /* Even parity generation/check */
#define SER1_MODE_ESD 0x40 /* External sync detect */
#define SER1_MODE_SCS 0x80 /* Single character sync */
/* Character length */
#define SER1_MODE_LENGTH_5 0x00
#define SER1_MODE_LENGTH_6 0x04
#define SER1_MODE_LENGTH_7 0x08
#define SER1_MODE_LENGTH_8 0x0C
/* Baud rate factor */
#define SER1_MODE_SYNC 0x00
#define SER1_MODE_CLOCKx1 0x01
#define SER1_MODE_CLOCKx16 0x02
#define SER1_MODE_CLOCKx64 0x03
/* Number of stop bits */
#define SER1_MODE_1_STOP 0x40
#define SER1_MODE_1_5_STOP 0x80
#define SER1_MODE_2_STOP 0xC0
/* Command bits */
#define SER1_COMMMAND_TxEN 0x01 /* Transmit enable */
#define SER1_COMMMAND_DTR 0x02 /* Data terminal ready */
#define SER1_COMMMAND_RxEN 0x04 /* Receive enable */
#define SER1_COMMMAND_SBRK 0x08 /* Send break character */
#define SER1_COMMMAND_ER 0x10 /* Error reset */
#define SER1_COMMMAND_RTS 0x20 /* Request to send */
#define SER1_COMMMAND_IR 0x40 /* Internal reset */
#define SER1_COMMMAND_EH 0x80 /* Enter hunt mode */
#define SER1_IO_o_TRANSMITTER_BUFFER 0x130
#define SER1_IO_o_FIFO_CONTROL 0x138
#define SER_FCR_DISABLE 0x00 /* Disable FIFO */
#define SER_FCR_ENABLE 0x01 /* Enable FIFO */
#define SER_FCR_RCVR_RESET 0x02 /* Clear receive FIFO */
#define SER_FCR_TXMT_RESET 0x04 /* Clear transmit FIFO */
/* Receive FIFO interrupt trigger level */
#define SER_FCR_1_BYTE_HIGH_WATER 0x00
#define SER_FCR_4_BYTE_HIGH_WATER 0x40
#define SER_FCR_8_BYTE_HIGH_WATER 0x80
#define SER_FCR_14_BYTE_HIGH_WATER 0xC0
#define SER1_IO_o_DIVISOR_LATCH 0x13A
#define SER1_DLR_BAUD_115200 0x01
#define SER1_DLR_BAUD_57600 0x02
#define SER1_DLR_BAUD_38400 0x03
#define SER1_DLR_BAUD_28800 0x04
#define SER1_DLR_BAUD_19200 0x06
#define SER1_DLR_BAUD_14400 0x08
#define SER1_DLR_BAUD_9600 0x0C
#define SER1_DLR_MODE_VFAST 0x80
#define SER1_DLR_MODE_LEGACY 0x00
/* COM2 (National Semiconductor 16550 UART) ***********************************/
/*
* UART registers and definitions
*/
#define SER2_IO_i_RECEIVER_BUFFER 0x238 /* If DLAB = 0 */
#define SER2_IO_i_DIVISOR_LATCH_LSB 0x238 /* If DLAB = 1 */
#define SER2_IO_i_INTERRUPT_EN 0x239 /* If DLAB = 0 */
#define SER2_IO_i_DIVISOR_LATCH_MSB 0x239 /* If DLAB = 1 */
#define SER2_IO_i_INTERRUPT_ID 0x23A
/* Bits 0-3 same as for COM1 */
#define SER2_IIR_MUST_BE_ZERO 0x30
#define SER2_IIR_NO_FIFO 0x00
#define SER2_IIR_HAS_FIFO 0x40
#define SER2_IIR_FIFOS_ENABLED 0xC0
#define SER2_IO_i_LINE_CONTROL 0x23B
#define SER2_IO_i_MODEM_CONTROL 0x23C
#define SER2_IO_i_LINE_STATUS 0x23D
#define SER2_LSR_DR 0x01 /* Data ready */
#define SER2_LSR_OE 0x02 /* Overrun error */
#define SER2_LSR_PE 0x04 /* Parity error */
#define SER2_LSR_FE 0x80 /* Framing error */
#define SER2_LSR_BI 0x80 /* Break interrupt */
#define SER2_LSR_THR_EMPTY 0x20 /* Transmit holding register empty */
#define SER2_LSR_TSR_EMPTY 0x40 /* Transmitter FIFO empty */
#define SER2_LSR_ERROR_IN_FIFO 0x80 /* FIFO error */
#define SER2_IO_i_MODEM_STATUS 0x23E
/* Bits 0-7 same as for COM1 */
#define SER2_IO_i_SCRATCH 0x23F
#define SER2_IO_o_TRANSMITTER_BUFFER 0x238 /* If DLAB = 0 */
#define SER2_IO_o_DIVISOR_LATCH_LSB 0x238 /* If DLAB = 1 */
#define SER2_DLR_BAUD_115200 0x0001
#define SER2_DLR_BAUD_57600 0x0002
#define SER2_DLR_BAUD_38400 0x0003
#define SER2_DLR_BAUD_19200 0x0006
#define SER2_DLR_BAUD_9600 0x000C
#define SER2_DLR_BAUD_4800 0x0018
#define SER2_DLR_BAUD_2400 0x0030
#define SER2_DLR_BAUD_1200 0x0060
#define SER2_DLR_BAUD_600 0x00C0
#define SER2_DLR_BAUD_300 0x0180
#define SER2_IO_o_DIVISOR_LATCH_MSB 0x239 /* If DLAB = 1 */
#define SER2_IO_o_INTERRUPT_EN 0x239 /* If DLAB = 0 */
#define SER2_IER_DATA_RECEIVED 0x01 /* Received data available */
#define SER2_IER_THR_EMPTY 0x02 /* Transmitter holding register empty */
#define SER2_IER_LSR_CHANGE 0x04 /* Receiver line register status change */
#define SER2_IER_MSR_CHANGE 0x08 /* Modem status register change */
#define SER2_IO_o_FIFO_CONTROL 0x23A
/* Bits 0-2, 6-7 same as for COM1 */
#define SER2_FCR_DMA_SELECT 0x04
#define SER2_IO_o_LINE_CONTROL 0x23B
/* Character length */
#define SER2_LCR_LENGTH_5 0x00
#define SER2_LCR_LENGTH_6 0x01
#define SER2_LCR_LENGTH_7 0x02
#define SER2_LCR_LENGTH_8 0x03
/* Number of stop bits */
#define SER2_LCR_ST1 0x00 /* 1 */
#define SER2_LCR_ST2 0x04 /* 1.5 - 2 */
/* Parity generate/check */
#define SER2_LCR_NO_PARITY 0x00
#define SER2_LCR_ODD_PARITY 0x08
#define SER2_LCR_EVEN_PARITY 0x18
#define SER2_LCR_MARK_PARITY 0x28
#define SER2_LCR_SPACE_PARITY 0x38
#define SER2_LCR_BREAK 0x40
#define SER2_LCR_DLAB 0x80 /* Divisor latch access bit */
#define SER2_IO_o_MODEM_CONTROL 0x23C
#define SER2_MCR_DTR_STATE 0x01 /* Data terminal ready */
#define SER2_MCR_RTS_STATE 0x02 /* Request to send */
#define SER2_MCR_OUT_1 0x04
#define SER2_MCR_OUT_2 0x08
#define SER2_MCR_LOOPBACK 0x10
#define SER2_IO_o_LINE_STATUS 0x23D
#define SER2_IO_o_SCRATCH 0x23F
#define SER2_CLOCK_RATE 115200

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sdk/include/reactos/drivers/pc98/sysport.h Normal file
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/*
* PROJECT: NEC PC-98 series onboard hardware
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: Intel 8255A PPI header file
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
*/
#pragma once
#define PPI_IO_o_PORT_C 0x35
#define PPI_IO_o_CONTROL 0x37
#define PPI_IO_i_PORT_A 0x31
#define PPI_IO_i_PORT_B 0x33
#define PPI_IO_i_PORT_C 0x35
typedef union _SYSTEM_CONTROL_PORT_A_REGISTER
{
struct
{
UCHAR DipSw2_1:1;
UCHAR DipSw2_2:1;
UCHAR DipSw2_3:1;
UCHAR DipSw2_4:1;
UCHAR DipSw2_5:1;
UCHAR DipSw2_6:1;
UCHAR DipSw2_7:1;
UCHAR DipSw2_8:1;
};
UCHAR Bits;
} SYSTEM_CONTROL_PORT_A_REGISTER, *PSYSTEM_CONTROL_PORT_A_REGISTER;
typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
{
struct
{
UCHAR RtcData:1;
/* NMI */
UCHAR ExtendedMemoryParityCheck:1;
UCHAR MemoryParityCheck:1;
UCHAR HighResolution:1;
UCHAR Int3:1;
UCHAR DataCarrierDetect:1;
UCHAR ClearToSend:1;
UCHAR RingIndicator:1;
};
UCHAR Bits;
} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
typedef union _SYSTEM_CONTROL_PORT_C_REGISTER
{
struct
{
UCHAR InterruptEnableRxReady:1;
UCHAR InterruptEnableTxEmpty:1;
UCHAR InterruptEnableTxReady:1;
UCHAR Timer1GateToSpeaker:1;
UCHAR Mcke:1;
UCHAR Shut1:1;
UCHAR PrinterStrobeSignal:1;
UCHAR Shut0:1;
};
UCHAR Bits;
} SYSTEM_CONTROL_PORT_C_REGISTER, *PSYSTEM_CONTROL_PORT_C_REGISTER;
typedef union _SYSTEM_CONTROL_PORT_REGISTER
{
struct
{
UCHAR InterruptEnableRxReady:1;
UCHAR InterruptEnableTxEmpty:1;
UCHAR InterruptEnableTxReady:1;
UCHAR Timer1GateToSpeaker:1;
UCHAR Mcke:1;
UCHAR Shut1:1;
UCHAR PrinterStrobeSignal:1;
UCHAR Shut0:1;
};
UCHAR Bits;
} SYSTEM_CONTROL_PORT_REGISTER, *PSYSTEM_CONTROL_PORT_REGISTER;