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[CPORTLIB][NTOS:INBV][KDCOM][FREELDR] Add ComPort library for NEC PC-98 series (#2407)
There are 2 known serial ports:
COM1 - based on Intel 8251A
COM2 - National Semiconductor 16550
This commit is contained in:
Dmitry Borisov
GitHub
parent
a6515e2b75
commit
222e79232c
12 changed files with 1104 additions and 1 deletions
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@ -33,7 +33,11 @@
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#define DEFAULT_BAUD_RATE 19200
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#if defined(_M_IX86) || defined(_M_AMD64)
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#if defined(SARCH_PC98)
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static const ULONG BaseArray[] = {0, 0x30, 0x238};
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#else
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static const ULONG BaseArray[] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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#endif
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#elif defined(_M_PPC)
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static const ULONG BaseArray[] = {0, 0x800003F8};
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#elif defined(_M_MIPS)
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@ -70,6 +70,42 @@ WinLdrPortInitialize(IN ULONG BaudRate,
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/* Set default baud rate */
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if (BaudRate == 0) BaudRate = 19200;
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#if defined(SARCH_PC98)
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/* Check if port or address given */
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if (PortNumber)
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{
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/* Pick correct address for port */
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if (!PortAddress)
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{
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if (PortNumber == 1)
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{
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PortAddress = (PUCHAR)0x30;
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}
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else
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{
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PortAddress = (PUCHAR)0x238;
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PortNumber = 2;
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}
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}
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}
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else
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{
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/* Pick correct port for address */
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PortAddress = (PUCHAR)0x30;
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if (CpDoesPortExist(PortAddress))
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{
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PortNumber = 1;
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}
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else
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{
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PortAddress = (PUCHAR)0x238;
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if (!CpDoesPortExist(PortAddress))
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return FALSE;
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PortNumber = 2;
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}
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}
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#else
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/* Check if port or address given */
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if (PortNumber)
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{
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@ -111,6 +147,7 @@ WinLdrPortInitialize(IN ULONG BaudRate,
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PortNumber = 1;
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}
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}
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#endif
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/* Not yet supported */
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ASSERT(LoaderRedirectionInformation.IsMMIODevice == FALSE);
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@ -173,6 +210,25 @@ WinLdrInitializeHeadlessPort(VOID)
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PortAddress = LoaderRedirectionInformation.PortAddress;
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BaudRate = LoaderRedirectionInformation.BaudRate;
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#if defined(SARCH_PC98)
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/* Pick a port address */
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if (PortNumber)
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{
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if (!PortAddress)
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{
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if (PortNumber == 2)
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LoaderRedirectionInformation.PortAddress = (PUCHAR)0x238;
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else
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LoaderRedirectionInformation.PortAddress = (PUCHAR)0x30;
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}
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}
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else
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{
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/* No number, so no EMS */
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WinLdrTerminalConnected = FALSE;
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return;
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}
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#else
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/* Pick a port address */
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if (PortNumber)
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{
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@ -204,6 +260,7 @@ WinLdrInitializeHeadlessPort(VOID)
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WinLdrTerminalConnected = FALSE;
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return;
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}
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#endif
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/* Call arch code to initialize the port */
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PortAddress = LoaderRedirectionInformation.PortAddress;
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@ -23,7 +23,11 @@
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#define DEFAULT_BAUD_RATE 19200
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#if defined(_M_IX86) || defined(_M_AMD64)
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#if defined(SARCH_PC98)
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const ULONG BaseArray[] = {0, 0x30, 0x238};
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#else
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const ULONG BaseArray[] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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#endif
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#elif defined(_M_PPC)
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const ULONG BaseArray[] = {0, 0x800003F8};
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#elif defined(_M_MIPS)
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@ -21,7 +21,11 @@
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#define DEFAULT_BAUD_RATE 19200
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#if defined(_M_IX86) || defined(_M_AMD64)
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#if defined(SARCH_PC98)
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const ULONG BaseArray[] = {0, 0x30, 0x238};
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#else
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const ULONG BaseArray[] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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#endif
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#elif defined(_M_PPC)
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const ULONG BaseArray[] = {0, 0x800003F8};
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#elif defined(_M_MIPS)
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@ -82,6 +82,42 @@ InbvPortInitialize(IN ULONG BaudRate,
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/* Set default baud rate */
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if (BaudRate == 0) BaudRate = 19200;
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#if defined(SARCH_PC98)
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/* Check if port or address given */
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if (PortNumber)
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{
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/* Pick correct address for port */
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if (!PortAddress)
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{
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if (PortNumber == 1)
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{
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PortAddress = (PUCHAR)0x30;
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}
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else
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{
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PortAddress = (PUCHAR)0x238;
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PortNumber = 2;
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}
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}
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}
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else
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{
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/* Pick correct port for address */
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PortAddress = (PUCHAR)0x30;
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if (CpDoesPortExist(PortAddress))
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{
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PortNumber = 1;
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}
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else
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{
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PortAddress = (PUCHAR)0x238;
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if (!CpDoesPortExist(PortAddress))
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return FALSE;
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PortNumber = 2;
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}
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}
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#else
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/* Check if port or address given */
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if (PortNumber)
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{
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@ -123,6 +159,7 @@ InbvPortInitialize(IN ULONG BaudRate,
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PortNumber = 1;
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}
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}
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#endif
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/* Initialize the port unless it's already up, and then return it */
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if (Port[PortNumber - 1].Address) return FALSE;
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@ -17,7 +17,11 @@
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#define DEFAULT_BAUD_RATE 19200
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#if defined(_M_IX86) || defined(_M_AMD64)
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#if defined(SARCH_PC98)
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const ULONG BaseArray[] = {0, 0x30, 0x238};
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#else
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const ULONG BaseArray[] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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#endif
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#elif defined(_M_PPC)
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const ULONG BaseArray[] = {0, 0x800003F8};
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#elif defined(_M_MIPS)
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28
sdk/include/reactos/drivers/pc98/cpu.h
Normal file
28
sdk/include/reactos/drivers/pc98/cpu.h
Normal file
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@ -0,0 +1,28 @@
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: CPU I/O ports header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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#define CPU_IO_o_RESET 0x0F
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#define CPU_IO_o_A20_UNMASK 0xF2
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#define CPU_IO_o_A20_CONTROL 0xF6
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#define CPU_A20_ENABLE 0x02
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#define CPU_A20_DISABLE 0x03
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/*
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* ARTIC (A Relative Time Indication Counter) - 24-bit binary up counter
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*/
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#define CPU_IO_o_ARTIC_DELAY 0x5F /* Constant delay (about 600 ns) */
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#define CPU_IO_i_ARTIC_0 0x5C
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#define CPU_IO_i_ARTIC_1 0x5D
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#define CPU_IO_i_ARTIC_2 0x5E
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#define CPU_IO_i_ARTIC_3 0x5F
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#define ARTIC_FREQUENCY 307200
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#define ARTIC_FREQUENCY_0_1 ARTIC_FREQUENCY
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#define ARTIC_FREQUENCY_2_3 (ARTIC_FREQUENCY >> 8)
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97
sdk/include/reactos/drivers/pc98/pit.h
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97
sdk/include/reactos/drivers/pc98/pit.h
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@ -0,0 +1,97 @@
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/*
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* PROJECT: NEC PC-98 series on-board hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Intel 8253A PIT header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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#define TIMER_CHANNEL0_DATA_PORT 0x71
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#define TIMER_CHANNEL1_DATA_PORT 0x73
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#define TIMER_CHANNEL2_DATA_PORT 0x75
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#define TIMER_CONTROL_PORT 0x77
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/* Tick rate of PIT depends on system clock frequency */
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#define TIMER_FREQUENCY_1 1996800 /* 8 MHz */
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#define TIMER_FREQUENCY_2 2457600 /* 10 MHz, 5 MHz */
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typedef enum _TIMER_OPERATING_MODES
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{
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/* Interrupt On Terminal Count */
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PitOperatingMode0,
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/* Hardware Re-triggerable One-Shot */
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PitOperatingMode1,
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/* Rate Generator */
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PitOperatingMode2,
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/* Square Wave Generator */
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PitOperatingMode3,
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/* Software Triggered Strobe */
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PitOperatingMode4,
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/* Hardware Triggered Strobe */
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PitOperatingMode5
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} TIMER_OPERATING_MODES;
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typedef enum _TIMER_ACCESS_MODES
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{
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PitAccessModeCounterLatch,
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PitAccessModeLow,
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PitAccessModeHigh,
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PitAccessModeLowHigh
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} TIMER_ACCESS_MODES;
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typedef enum _TIMER_CHANNELS
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{
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/* IRQ 0 */
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PitChannel0,
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/* PC Speaker */
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PitChannel1,
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/* RS-232 chipset */
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PitChannel2,
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/* Execute multiple latch command */
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MultipleLatch
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} TIMER_CHANNELS;
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typedef union _TIMER_CONTROL_PORT_REGISTER
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{
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struct
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{
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UCHAR BcdMode:1;
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UCHAR OperatingMode:3;
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UCHAR AccessMode:2;
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UCHAR Channel:2;
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};
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UCHAR Bits;
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} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
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FORCEINLINE
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ULONG
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Read8253Timer(TIMER_CHANNELS TimerChannel)
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{
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ULONG Count;
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WRITE_PORT_UCHAR((PUCHAR)TIMER_CONTROL_PORT, (TimerChannel << 6) | PitAccessModeCounterLatch);
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Count = READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2));
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Count |= READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2)) << 8;
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return Count;
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}
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FORCEINLINE
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VOID
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Write8253Timer(
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TIMER_CONTROL_PORT_REGISTER TimerControl,
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USHORT Count)
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{
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WRITE_PORT_UCHAR((PUCHAR)TIMER_CONTROL_PORT, TimerControl.Bits);
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WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), Count & 0xFF);
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WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), (Count >> 8) & 0xFF);
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}
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184
sdk/include/reactos/drivers/pc98/serial.h
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184
sdk/include/reactos/drivers/pc98/serial.h
Normal file
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@ -0,0 +1,184 @@
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: UART header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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/* COM1 (Intel 8251A-based UART) **********************************************/
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/*
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* UART registers and definitions
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*/
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#define SER1_IO_i_DATA 0x030
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#define SER1_IO_i_STATUS 0x032
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#define SER1_STATUS_TxRDY 0x01 /* Transmitter ready */
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#define SER1_STATUS_RxRDY 0x02 /* Receiver ready */
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#define SER1_STATUS_TxEMPTY 0x04 /* Transmitter empty */
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#define SER1_STATUS_PE 0x08 /* Parity error */
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#define SER1_STATUS_OE 0x10 /* Overrun error */
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#define SER1_STATUS_FE 0x20 /* Framing error */
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#define SER1_STATUS_SYNDET 0x40 /* Sync detect / Break detect */
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#define SER1_STATUS_DSR 0x80 /* Data set ready */
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#define SER1_IO_i_RECEIVER_BUFFER 0x130
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#define SER1_IO_i_LINE_STATUS 0x132
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#define SER1_LSR_TxEMPTY 0x01 /* Transmitter empty */
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#define SER1_LSR_TxRDY 0x02 /* Transmitter ready */
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#define SER1_LSR_RxRDY 0x04 /* Receiver ready */
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#define SER1_LSR_OE 0x10 /* Overrun error */
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#define SER1_LSR_PE 0x20 /* Parity error */
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#define SER1_LSR_BI 0x80 /* Break detect */
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#define SER1_IO_i_MODEM_STATUS 0x134
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#define SER_MSR_CTS_CHANGED 0x01 /* Change in clear to send */
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#define SER_MSR_DSR_CHANGED 0x02 /* Change in data set ready */
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#define SER_MSR_RI_CHANGED 0x04 /* Trailing edge ring indicator */
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#define SER_MSR_DCD_CHANGED 0x08 /* Change in carrier detect */
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#define SER_MSR_CTS 0x10 /* Clear to send */
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#define SER_MSR_DSR 0x20 /* Data set ready */
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#define SER_MSR_RI 0x40 /* Ring indicator */
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#define SER_MSR_DCD 0x80 /* Data carrier detect */
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#define SER1_IO_i_INTERRUPT_ID 0x136
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#define SER_IIR_MS 0x00 /* Modem status change */
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#define SER_IIR_THR 0x02 /* Transmitter holding register empty */
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#define SER_IIR_RDA 0x04 /* Received data acailable */
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#define SER_IIR_RLS 0x06 /* Receiver line status change */
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#define SER_IIR_CTI 0x0C /* Character timeout */
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#define SER_IIR_ID_MASK 0x0F
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#define SER_IIR_SELF 0x01 /* No interrupt pending */
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#define SER1_IIR_MUST_BE_ZERO 0x20
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#define SER1_IIR_FIFOS_ENABLED 0x40 /* Toggles for each read */
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#define SER1_IO_i_FIFO_CONTROL 0x138
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#define SER1_IO_i_DIVISOR_LATCH 0x13A
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#define SER1_IO_o_DATA 0x030
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#define SER1_IO_o_MODE_COMMAND 0x032
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/* Parity generate/check */
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#define SER1_MODE_PEN 0x10 /* Parity enable */
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#define SER1_MODE_EP 0x20 /* Even parity generation/check */
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#define SER1_MODE_ESD 0x40 /* External sync detect */
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#define SER1_MODE_SCS 0x80 /* Single character sync */
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/* Character length */
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#define SER1_MODE_LENGTH_5 0x00
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#define SER1_MODE_LENGTH_6 0x04
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#define SER1_MODE_LENGTH_7 0x08
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#define SER1_MODE_LENGTH_8 0x0C
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/* Baud rate factor */
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#define SER1_MODE_SYNC 0x00
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#define SER1_MODE_CLOCKx1 0x01
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#define SER1_MODE_CLOCKx16 0x02
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#define SER1_MODE_CLOCKx64 0x03
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/* Number of stop bits */
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#define SER1_MODE_1_STOP 0x40
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#define SER1_MODE_1_5_STOP 0x80
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#define SER1_MODE_2_STOP 0xC0
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/* Command bits */
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#define SER1_COMMMAND_TxEN 0x01 /* Transmit enable */
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#define SER1_COMMMAND_DTR 0x02 /* Data terminal ready */
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#define SER1_COMMMAND_RxEN 0x04 /* Receive enable */
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#define SER1_COMMMAND_SBRK 0x08 /* Send break character */
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#define SER1_COMMMAND_ER 0x10 /* Error reset */
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#define SER1_COMMMAND_RTS 0x20 /* Request to send */
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#define SER1_COMMMAND_IR 0x40 /* Internal reset */
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#define SER1_COMMMAND_EH 0x80 /* Enter hunt mode */
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#define SER1_IO_o_TRANSMITTER_BUFFER 0x130
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#define SER1_IO_o_FIFO_CONTROL 0x138
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#define SER_FCR_DISABLE 0x00 /* Disable FIFO */
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#define SER_FCR_ENABLE 0x01 /* Enable FIFO */
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#define SER_FCR_RCVR_RESET 0x02 /* Clear receive FIFO */
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#define SER_FCR_TXMT_RESET 0x04 /* Clear transmit FIFO */
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/* Receive FIFO interrupt trigger level */
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#define SER_FCR_1_BYTE_HIGH_WATER 0x00
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#define SER_FCR_4_BYTE_HIGH_WATER 0x40
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#define SER_FCR_8_BYTE_HIGH_WATER 0x80
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#define SER_FCR_14_BYTE_HIGH_WATER 0xC0
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#define SER1_IO_o_DIVISOR_LATCH 0x13A
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#define SER1_DLR_BAUD_115200 0x01
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#define SER1_DLR_BAUD_57600 0x02
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#define SER1_DLR_BAUD_38400 0x03
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#define SER1_DLR_BAUD_28800 0x04
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#define SER1_DLR_BAUD_19200 0x06
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#define SER1_DLR_BAUD_14400 0x08
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#define SER1_DLR_BAUD_9600 0x0C
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#define SER1_DLR_MODE_VFAST 0x80
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#define SER1_DLR_MODE_LEGACY 0x00
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/* COM2 (National Semiconductor 16550 UART) ***********************************/
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/*
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* UART registers and definitions
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*/
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#define SER2_IO_i_RECEIVER_BUFFER 0x238 /* If DLAB = 0 */
|
||||
#define SER2_IO_i_DIVISOR_LATCH_LSB 0x238 /* If DLAB = 1 */
|
||||
#define SER2_IO_i_INTERRUPT_EN 0x239 /* If DLAB = 0 */
|
||||
#define SER2_IO_i_DIVISOR_LATCH_MSB 0x239 /* If DLAB = 1 */
|
||||
#define SER2_IO_i_INTERRUPT_ID 0x23A
|
||||
/* Bits 0-3 same as for COM1 */
|
||||
#define SER2_IIR_MUST_BE_ZERO 0x30
|
||||
#define SER2_IIR_NO_FIFO 0x00
|
||||
#define SER2_IIR_HAS_FIFO 0x40
|
||||
#define SER2_IIR_FIFOS_ENABLED 0xC0
|
||||
#define SER2_IO_i_LINE_CONTROL 0x23B
|
||||
#define SER2_IO_i_MODEM_CONTROL 0x23C
|
||||
#define SER2_IO_i_LINE_STATUS 0x23D
|
||||
#define SER2_LSR_DR 0x01 /* Data ready */
|
||||
#define SER2_LSR_OE 0x02 /* Overrun error */
|
||||
#define SER2_LSR_PE 0x04 /* Parity error */
|
||||
#define SER2_LSR_FE 0x80 /* Framing error */
|
||||
#define SER2_LSR_BI 0x80 /* Break interrupt */
|
||||
#define SER2_LSR_THR_EMPTY 0x20 /* Transmit holding register empty */
|
||||
#define SER2_LSR_TSR_EMPTY 0x40 /* Transmitter FIFO empty */
|
||||
#define SER2_LSR_ERROR_IN_FIFO 0x80 /* FIFO error */
|
||||
#define SER2_IO_i_MODEM_STATUS 0x23E
|
||||
/* Bits 0-7 same as for COM1 */
|
||||
#define SER2_IO_i_SCRATCH 0x23F
|
||||
|
||||
#define SER2_IO_o_TRANSMITTER_BUFFER 0x238 /* If DLAB = 0 */
|
||||
#define SER2_IO_o_DIVISOR_LATCH_LSB 0x238 /* If DLAB = 1 */
|
||||
#define SER2_DLR_BAUD_115200 0x0001
|
||||
#define SER2_DLR_BAUD_57600 0x0002
|
||||
#define SER2_DLR_BAUD_38400 0x0003
|
||||
#define SER2_DLR_BAUD_19200 0x0006
|
||||
#define SER2_DLR_BAUD_9600 0x000C
|
||||
#define SER2_DLR_BAUD_4800 0x0018
|
||||
#define SER2_DLR_BAUD_2400 0x0030
|
||||
#define SER2_DLR_BAUD_1200 0x0060
|
||||
#define SER2_DLR_BAUD_600 0x00C0
|
||||
#define SER2_DLR_BAUD_300 0x0180
|
||||
#define SER2_IO_o_DIVISOR_LATCH_MSB 0x239 /* If DLAB = 1 */
|
||||
#define SER2_IO_o_INTERRUPT_EN 0x239 /* If DLAB = 0 */
|
||||
#define SER2_IER_DATA_RECEIVED 0x01 /* Received data available */
|
||||
#define SER2_IER_THR_EMPTY 0x02 /* Transmitter holding register empty */
|
||||
#define SER2_IER_LSR_CHANGE 0x04 /* Receiver line register status change */
|
||||
#define SER2_IER_MSR_CHANGE 0x08 /* Modem status register change */
|
||||
#define SER2_IO_o_FIFO_CONTROL 0x23A
|
||||
/* Bits 0-2, 6-7 same as for COM1 */
|
||||
#define SER2_FCR_DMA_SELECT 0x04
|
||||
#define SER2_IO_o_LINE_CONTROL 0x23B
|
||||
/* Character length */
|
||||
#define SER2_LCR_LENGTH_5 0x00
|
||||
#define SER2_LCR_LENGTH_6 0x01
|
||||
#define SER2_LCR_LENGTH_7 0x02
|
||||
#define SER2_LCR_LENGTH_8 0x03
|
||||
/* Number of stop bits */
|
||||
#define SER2_LCR_ST1 0x00 /* 1 */
|
||||
#define SER2_LCR_ST2 0x04 /* 1.5 - 2 */
|
||||
/* Parity generate/check */
|
||||
#define SER2_LCR_NO_PARITY 0x00
|
||||
#define SER2_LCR_ODD_PARITY 0x08
|
||||
#define SER2_LCR_EVEN_PARITY 0x18
|
||||
#define SER2_LCR_MARK_PARITY 0x28
|
||||
#define SER2_LCR_SPACE_PARITY 0x38
|
||||
#define SER2_LCR_BREAK 0x40
|
||||
#define SER2_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
#define SER2_IO_o_MODEM_CONTROL 0x23C
|
||||
#define SER2_MCR_DTR_STATE 0x01 /* Data terminal ready */
|
||||
#define SER2_MCR_RTS_STATE 0x02 /* Request to send */
|
||||
#define SER2_MCR_OUT_1 0x04
|
||||
#define SER2_MCR_OUT_2 0x08
|
||||
#define SER2_MCR_LOOPBACK 0x10
|
||||
#define SER2_IO_o_LINE_STATUS 0x23D
|
||||
#define SER2_IO_o_SCRATCH 0x23F
|
||||
|
||||
#define SER2_CLOCK_RATE 115200
|
||||
82
sdk/include/reactos/drivers/pc98/sysport.h
Normal file
82
sdk/include/reactos/drivers/pc98/sysport.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* PROJECT: NEC PC-98 series onboard hardware
|
||||
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
|
||||
* PURPOSE: Intel 8255A PPI header file
|
||||
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define PPI_IO_o_PORT_C 0x35
|
||||
#define PPI_IO_o_CONTROL 0x37
|
||||
|
||||
#define PPI_IO_i_PORT_A 0x31
|
||||
#define PPI_IO_i_PORT_B 0x33
|
||||
#define PPI_IO_i_PORT_C 0x35
|
||||
|
||||
typedef union _SYSTEM_CONTROL_PORT_A_REGISTER
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR DipSw2_1:1;
|
||||
UCHAR DipSw2_2:1;
|
||||
UCHAR DipSw2_3:1;
|
||||
UCHAR DipSw2_4:1;
|
||||
UCHAR DipSw2_5:1;
|
||||
UCHAR DipSw2_6:1;
|
||||
UCHAR DipSw2_7:1;
|
||||
UCHAR DipSw2_8:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} SYSTEM_CONTROL_PORT_A_REGISTER, *PSYSTEM_CONTROL_PORT_A_REGISTER;
|
||||
|
||||
typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR RtcData:1;
|
||||
|
||||
/* NMI */
|
||||
UCHAR ExtendedMemoryParityCheck:1;
|
||||
UCHAR MemoryParityCheck:1;
|
||||
|
||||
UCHAR HighResolution:1;
|
||||
UCHAR Int3:1;
|
||||
UCHAR DataCarrierDetect:1;
|
||||
UCHAR ClearToSend:1;
|
||||
UCHAR RingIndicator:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
|
||||
|
||||
typedef union _SYSTEM_CONTROL_PORT_C_REGISTER
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR InterruptEnableRxReady:1;
|
||||
UCHAR InterruptEnableTxEmpty:1;
|
||||
UCHAR InterruptEnableTxReady:1;
|
||||
UCHAR Timer1GateToSpeaker:1;
|
||||
UCHAR Mcke:1;
|
||||
UCHAR Shut1:1;
|
||||
UCHAR PrinterStrobeSignal:1;
|
||||
UCHAR Shut0:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} SYSTEM_CONTROL_PORT_C_REGISTER, *PSYSTEM_CONTROL_PORT_C_REGISTER;
|
||||
|
||||
typedef union _SYSTEM_CONTROL_PORT_REGISTER
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR InterruptEnableRxReady:1;
|
||||
UCHAR InterruptEnableTxEmpty:1;
|
||||
UCHAR InterruptEnableTxReady:1;
|
||||
UCHAR Timer1GateToSpeaker:1;
|
||||
UCHAR Mcke:1;
|
||||
UCHAR Shut1:1;
|
||||
UCHAR PrinterStrobeSignal:1;
|
||||
UCHAR Shut0:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} SYSTEM_CONTROL_PORT_REGISTER, *PSYSTEM_CONTROL_PORT_REGISTER;
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
|
||||
add_library(cportlib cport.c)
|
||||
if(SARCH STREQUAL "pc98")
|
||||
add_library(cportlib cport_pc98.c)
|
||||
else()
|
||||
add_library(cportlib cport.c)
|
||||
endif()
|
||||
add_dependencies(cportlib xdk)
|
||||
|
|
|
|||
598
sdk/lib/cportlib/cport_pc98.c
Normal file
598
sdk/lib/cportlib/cport_pc98.c
Normal file
|
|
@ -0,0 +1,598 @@
|
|||
/*
|
||||
* PROJECT: ReactOS ComPort Library for NEC PC-98 series
|
||||
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
|
||||
* PURPOSE: Provides a serial port library for KDCOM, INIT, and FREELDR
|
||||
* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
|
||||
*/
|
||||
|
||||
/* Note: ns16550 code from cportlib.c */
|
||||
|
||||
/* INCLUDES *******************************************************************/
|
||||
|
||||
#include <intrin.h>
|
||||
#include <ioaccess.h>
|
||||
#include <ntstatus.h>
|
||||
#include <ntstatus.h>
|
||||
#include <cportlib/cportlib.h>
|
||||
#include <drivers/pc98/serial.h>
|
||||
#include <drivers/pc98/sysport.h>
|
||||
#include <drivers/pc98/pit.h>
|
||||
#include <drivers/pc98/cpu.h>
|
||||
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
/* GLOBALS ********************************************************************/
|
||||
|
||||
#define TIMEOUT_COUNT 1024 * 200
|
||||
|
||||
static struct
|
||||
{
|
||||
PUCHAR Address;
|
||||
BOOLEAN HasFifo;
|
||||
BOOLEAN FifoEnabled;
|
||||
UCHAR RingIndicator;
|
||||
} Rs232ComPort[] =
|
||||
{
|
||||
{ (PUCHAR)0x030, FALSE, FALSE, 0 },
|
||||
{ (PUCHAR)0x238, FALSE, FALSE, 0 }
|
||||
};
|
||||
|
||||
static BOOLEAN IsNekoProject = FALSE;
|
||||
|
||||
/* FUNCTIONS ******************************************************************/
|
||||
|
||||
static BOOLEAN
|
||||
CpIsNekoProject(VOID)
|
||||
{
|
||||
UCHAR Input[3] = "NP2";
|
||||
UCHAR Output[3];
|
||||
UCHAR i;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x7EF, Input[i]);
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
Output[i] = READ_PORT_UCHAR((PUCHAR)0x7EF);
|
||||
|
||||
return (memcmp(Input, Output, 3) == 0);
|
||||
}
|
||||
|
||||
static VOID
|
||||
CpWait(VOID)
|
||||
{
|
||||
UCHAR i;
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
WRITE_PORT_UCHAR((PUCHAR)CPU_IO_o_ARTIC_DELAY, 0);
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
CpEnableFifo(
|
||||
IN PUCHAR Address,
|
||||
IN BOOLEAN Enable)
|
||||
{
|
||||
/* Set FIFO and clear the receive/transmit buffers */
|
||||
if (Address == Rs232ComPort[0].Address && Rs232ComPort[0].HasFifo)
|
||||
{
|
||||
if (Enable)
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_FIFO_CONTROL,
|
||||
SER_FCR_ENABLE | SER_FCR_RCVR_RESET | SER_FCR_TXMT_RESET);
|
||||
else
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_FIFO_CONTROL, SER_FCR_DISABLE);
|
||||
Rs232ComPort[0].FifoEnabled = Enable;
|
||||
}
|
||||
else if (Address == Rs232ComPort[1].Address && Rs232ComPort[1].HasFifo)
|
||||
{
|
||||
if (Enable)
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_FIFO_CONTROL,
|
||||
SER_FCR_ENABLE | SER_FCR_RCVR_RESET | SER_FCR_TXMT_RESET);
|
||||
else
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_FIFO_CONTROL, SER_FCR_DISABLE);
|
||||
Rs232ComPort[1].FifoEnabled = Enable;
|
||||
}
|
||||
CpWait();
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
CpSetBaud(
|
||||
IN PCPPORT Port,
|
||||
IN ULONG BaudRate)
|
||||
{
|
||||
UCHAR Lcr;
|
||||
USHORT Count;
|
||||
TIMER_CONTROL_PORT_REGISTER TimerControl;
|
||||
|
||||
if (Port->Address == Rs232ComPort[0].Address)
|
||||
{
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_DIVISOR_LATCH, SER1_DLR_MODE_LEGACY);
|
||||
|
||||
TimerControl.BcdMode = FALSE;
|
||||
TimerControl.OperatingMode = PitOperatingMode3;
|
||||
TimerControl.AccessMode = PitAccessModeLowHigh;
|
||||
TimerControl.Channel = PitChannel2;
|
||||
if (IsNekoProject)
|
||||
{
|
||||
/* The horrible text input lag happens by about 6 seconds on my PC */
|
||||
Count = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
Count = (READ_PORT_UCHAR((PUCHAR)0x42) & 0x20) ?
|
||||
(TIMER_FREQUENCY_1 / (BaudRate * 16)) : (TIMER_FREQUENCY_2 / (BaudRate * 16));
|
||||
}
|
||||
Write8253Timer(TimerControl, Count);
|
||||
|
||||
/* Save baud rate in port */
|
||||
Port->BaudRate = BaudRate;
|
||||
}
|
||||
else if (Port->Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
/* Set the DLAB on */
|
||||
Lcr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_LINE_CONTROL);
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, Lcr | SER2_LCR_DLAB);
|
||||
|
||||
/* Set the baud rate */
|
||||
Count = SER2_CLOCK_RATE / BaudRate;
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_DIVISOR_LATCH_LSB, Count & 0xFF);
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_DIVISOR_LATCH_MSB, (Count >> 8) & 0xFF);
|
||||
|
||||
/* Reset DLAB */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, Lcr & ~SER2_LCR_DLAB);
|
||||
|
||||
/* Save baud rate in port */
|
||||
Port->BaudRate = BaudRate;
|
||||
}
|
||||
}
|
||||
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
CpInitialize(
|
||||
IN PCPPORT Port,
|
||||
IN PUCHAR Address,
|
||||
IN ULONG BaudRate)
|
||||
{
|
||||
SYSTEM_CONTROL_PORT_C_REGISTER SystemControl;
|
||||
UCHAR FifoStatus;
|
||||
|
||||
if (Port == NULL || Address == NULL || BaudRate == 0)
|
||||
return STATUS_INVALID_PARAMETER;
|
||||
|
||||
if (!CpDoesPortExist(Address))
|
||||
return STATUS_NOT_FOUND;
|
||||
|
||||
/* Initialize port data */
|
||||
Port->Address = Address;
|
||||
Port->BaudRate = 0;
|
||||
Port->Flags = 0;
|
||||
|
||||
IsNekoProject = CpIsNekoProject();
|
||||
|
||||
if (Port->Address == Rs232ComPort[0].Address)
|
||||
{
|
||||
/* FIFO test */
|
||||
FifoStatus = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID) & SER1_IIR_FIFOS_ENABLED;
|
||||
CpWait();
|
||||
Rs232ComPort[0].HasFifo = ((READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID) & SER1_IIR_FIFOS_ENABLED) != FifoStatus);
|
||||
|
||||
/* Disable the interrupts */
|
||||
SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_C);
|
||||
SystemControl.InterruptEnableRxReady = FALSE;
|
||||
SystemControl.InterruptEnableTxEmpty = FALSE;
|
||||
SystemControl.InterruptEnableTxReady = FALSE;
|
||||
WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
|
||||
|
||||
/* Turn off FIFO */
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
CpEnableFifo(Address, FALSE);
|
||||
|
||||
/* Set the baud rate */
|
||||
CpSetBaud(Port, BaudRate);
|
||||
|
||||
/* Software reset */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
|
||||
CpWait();
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
|
||||
CpWait();
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, 0);
|
||||
CpWait();
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND, SER1_COMMMAND_IR);
|
||||
CpWait();
|
||||
|
||||
/* Mode instruction - asynchronous mode, 8 data bits, 1 stop bit, no parity, 16x clock divisor */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
|
||||
SER1_MODE_LENGTH_8 | SER1_MODE_1_STOP | SER1_MODE_CLOCKx16);
|
||||
CpWait();
|
||||
|
||||
/* Command instruction - transmit enable, turn on DTR and RTS, receive enable, clear error flag */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
|
||||
SER1_COMMMAND_TxEN | SER1_COMMMAND_DTR |
|
||||
SER1_COMMMAND_RxEN | SER1_COMMMAND_ER | SER1_COMMMAND_RTS);
|
||||
CpWait();
|
||||
|
||||
/* Disable the interrupts again */
|
||||
WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
|
||||
|
||||
/* Turn on FIFO */
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
CpEnableFifo(Address, TRUE);
|
||||
|
||||
/* Read junk out of the data register */
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_RECEIVER_BUFFER);
|
||||
else
|
||||
(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_DATA);
|
||||
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
else if (Port->Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
/* Disable the interrupts */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL, 0);
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_INTERRUPT_EN, 0);
|
||||
|
||||
/* Turn on DTR, RTS and OUT2 */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
|
||||
SER2_MCR_DTR_STATE | SER2_MCR_RTS_STATE | SER2_MCR_OUT_2);
|
||||
|
||||
/* Set the baud rate */
|
||||
CpSetBaud(Port, BaudRate);
|
||||
|
||||
/* Set 8 data bits, 1 stop bit, no parity, no break */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_LINE_CONTROL,
|
||||
SER2_LCR_LENGTH_8 | SER2_LCR_ST1 | SER2_LCR_NO_PARITY);
|
||||
|
||||
/* FIFO test */
|
||||
Rs232ComPort[1].HasFifo = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_INTERRUPT_ID) & SER2_IIR_HAS_FIFO;
|
||||
|
||||
/* Turn on FIFO */
|
||||
if (Rs232ComPort[1].HasFifo)
|
||||
CpEnableFifo(Address, TRUE);
|
||||
|
||||
/* Read junk out of the RBR */
|
||||
(VOID)READ_PORT_UCHAR((PUCHAR)SER2_IO_i_RECEIVER_BUFFER);
|
||||
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
return STATUS_NOT_FOUND;
|
||||
}
|
||||
|
||||
static BOOLEAN
|
||||
ComPortTest1(IN PUCHAR Address)
|
||||
{
|
||||
/*
|
||||
* See "Building Hardware and Firmware to Complement Microsoft Windows Headless Operation"
|
||||
* Out-of-Band Management Port Device Requirements:
|
||||
* The device must act as a 16550 or 16450 UART.
|
||||
* Windows Server 2003 will test this device using the following process:
|
||||
* 1. Save off the current modem status register.
|
||||
* 2. Place the UART into diagnostic mode (The UART is placed into loopback mode
|
||||
* by writing SERIAL_MCR_LOOP to the modem control register).
|
||||
* 3. The modem status register is read and the high bits are checked. This means
|
||||
* SERIAL_MSR_CTS, SERIAL_MSR_DSR, SERIAL_MSR_RI and SERIAL_MSR_DCD should
|
||||
* all be clear.
|
||||
* 4. Place the UART in diagnostic mode and turn on OUTPUT (Loopback Mode and
|
||||
* OUTPUT are both turned on by writing (SERIAL_MCR_LOOP | SERIAL_MCR_OUT1)
|
||||
* to the modem control register).
|
||||
* 5. The modem status register is read and the ring indicator is checked.
|
||||
* This means SERIAL_MSR_RI should be set.
|
||||
* 6. Restore original modem status register.
|
||||
*
|
||||
* REMARK: Strangely enough, the Virtual PC 2007 virtual machine
|
||||
* doesn't pass this test.
|
||||
*/
|
||||
|
||||
BOOLEAN RetVal = FALSE;
|
||||
UCHAR Mcr, Msr;
|
||||
|
||||
/* Save the Modem Control Register */
|
||||
Mcr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_CONTROL);
|
||||
|
||||
/* Enable loop (diagnostic) mode (set Bit 4 of the MCR) */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, SER2_MCR_LOOPBACK);
|
||||
|
||||
/* Clear all modem output bits */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, SER2_MCR_LOOPBACK);
|
||||
|
||||
/* Read the Modem Status Register */
|
||||
Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
|
||||
|
||||
/*
|
||||
* The upper nibble of the MSR (modem output bits) must be
|
||||
* equal to the lower nibble of the MCR (modem input bits).
|
||||
*/
|
||||
if ((Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD)) == 0x00)
|
||||
{
|
||||
/* Set all modem output bits */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
|
||||
SER2_MCR_OUT_1 | SER2_MCR_LOOPBACK); // Windows
|
||||
/* ReactOS
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
|
||||
SER2_MCR_DTR_STATE | SER2_MCR_RTS_STATE |
|
||||
SER2_MCR_OUT_1 | SER2_MCR_OUT_2 | SER2_MCR_LOOPBACK);
|
||||
*/
|
||||
|
||||
/* Read the Modem Status Register */
|
||||
Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
|
||||
|
||||
/*
|
||||
* The upper nibble of the MSR (modem output bits) must be
|
||||
* equal to the lower nibble of the MCR (modem input bits).
|
||||
*/
|
||||
if (Msr & SER_MSR_RI) // Windows
|
||||
// if (Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD) == 0xF0) // ReactOS
|
||||
{
|
||||
RetVal = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore the MCR */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL, Mcr);
|
||||
|
||||
return RetVal;
|
||||
}
|
||||
|
||||
static BOOLEAN
|
||||
ComPortTest2(IN PUCHAR Address)
|
||||
{
|
||||
/*
|
||||
* This test checks whether the 16450/16550 scratch register is available.
|
||||
* If not, the serial port is considered as unexisting.
|
||||
*/
|
||||
|
||||
UCHAR Byte = 0;
|
||||
|
||||
do
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_SCRATCH, Byte);
|
||||
|
||||
if (READ_PORT_UCHAR((PUCHAR)SER2_IO_i_SCRATCH) != Byte)
|
||||
return FALSE;
|
||||
|
||||
}
|
||||
while (++Byte != 0);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
NTAPI
|
||||
CpDoesPortExist(IN PUCHAR Address)
|
||||
{
|
||||
UCHAR Data, Status;
|
||||
|
||||
if (Address == Rs232ComPort[0].Address || Address == (PUCHAR)0x41)
|
||||
{
|
||||
Data = READ_PORT_UCHAR(Address);
|
||||
Status = READ_PORT_UCHAR(Address + 2);
|
||||
if ((Data & Status) == 0xFF || (Data | Status) == 0x00)
|
||||
return FALSE;
|
||||
else
|
||||
return TRUE;
|
||||
}
|
||||
else if (Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
return (ComPortTest1(Address) || ComPortTest2(Address));
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UCHAR
|
||||
NTAPI
|
||||
CpReadLsr(
|
||||
IN PCPPORT Port,
|
||||
IN UCHAR ExpectedValue)
|
||||
{
|
||||
UCHAR Lsr, Msr;
|
||||
SYSTEM_CONTROL_PORT_B_REGISTER SystemControl;
|
||||
|
||||
if (Port->Address == Rs232ComPort[0].Address)
|
||||
{
|
||||
/* Read the LSR and check if the expected value is present */
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
{
|
||||
Lsr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_LINE_STATUS);
|
||||
if (!(Lsr & ExpectedValue))
|
||||
{
|
||||
Msr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_MODEM_STATUS);
|
||||
|
||||
/* If the ring indicator reaches 3, we've seen this on/off twice */
|
||||
Rs232ComPort[0].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
|
||||
if (Rs232ComPort[0].RingIndicator == 3)
|
||||
Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Lsr = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_STATUS);
|
||||
if (!(Lsr & ExpectedValue))
|
||||
{
|
||||
SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_B);
|
||||
|
||||
/* If the ring indicator reaches 3, we've seen this on/off twice */
|
||||
Rs232ComPort[0].RingIndicator |= SystemControl.RingIndicator ? 1 : 2;
|
||||
if (Rs232ComPort[0].RingIndicator == 3)
|
||||
Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
|
||||
}
|
||||
}
|
||||
|
||||
return Lsr;
|
||||
}
|
||||
else if (Port->Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
/* Read the LSR and check if the expected value is present */
|
||||
Lsr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_LINE_STATUS);
|
||||
if (!(Lsr & ExpectedValue))
|
||||
{
|
||||
Msr = READ_PORT_UCHAR((PUCHAR)SER2_IO_i_MODEM_STATUS);
|
||||
|
||||
/* If the indicator reaches 3, we've seen this on/off twice */
|
||||
Rs232ComPort[1].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
|
||||
if (Rs232ComPort[1].RingIndicator == 3)
|
||||
Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
|
||||
}
|
||||
|
||||
return Lsr;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
USHORT
|
||||
NTAPI
|
||||
CpGetByte(
|
||||
IN PCPPORT Port,
|
||||
OUT PUCHAR Byte,
|
||||
IN BOOLEAN Wait,
|
||||
IN BOOLEAN Poll)
|
||||
{
|
||||
UCHAR Lsr;
|
||||
ULONG LimitCount = Wait ? TIMEOUT_COUNT : 1;
|
||||
UCHAR SuccessFlags, ErrorFlags;
|
||||
BOOLEAN FifoEnabled;
|
||||
|
||||
/* Handle early read-before-init */
|
||||
if (!Port->Address)
|
||||
return CP_GET_NODATA;
|
||||
|
||||
if (Port->Address == Rs232ComPort[0].Address)
|
||||
{
|
||||
SuccessFlags = Rs232ComPort[0].HasFifo ? SER1_LSR_RxRDY : SER1_STATUS_RxRDY;
|
||||
ErrorFlags = Rs232ComPort[0].HasFifo ? (SER1_LSR_PE | SER1_LSR_OE) :
|
||||
(SER1_STATUS_FE | SER1_STATUS_PE | SER1_STATUS_OE);
|
||||
|
||||
/* If "wait" mode enabled, spin many times, otherwise attempt just once */
|
||||
while (LimitCount--)
|
||||
{
|
||||
/* Read LSR for data ready */
|
||||
Lsr = CpReadLsr(Port, SuccessFlags);
|
||||
if (Lsr & SuccessFlags)
|
||||
{
|
||||
/* If an error happened, clear the byte and fail */
|
||||
if (Lsr & ErrorFlags)
|
||||
{
|
||||
/* Save the last FIFO state */
|
||||
FifoEnabled = Rs232ComPort[0].FifoEnabled;
|
||||
|
||||
/* Turn off FIFO */
|
||||
if (FifoEnabled)
|
||||
CpEnableFifo(Port->Address, FALSE);
|
||||
|
||||
/* Clear error flag */
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_MODE_COMMAND,
|
||||
SER1_COMMMAND_TxEN | SER1_COMMMAND_DTR |
|
||||
SER1_COMMMAND_RxEN | SER1_COMMMAND_ER | SER1_COMMMAND_RTS);
|
||||
|
||||
/* Turn on FIFO */
|
||||
if (FifoEnabled)
|
||||
CpEnableFifo(Port->Address, TRUE);
|
||||
|
||||
*Byte = 0;
|
||||
return CP_GET_ERROR;
|
||||
}
|
||||
|
||||
/* If only polling was requested by caller, return now */
|
||||
if (Poll)
|
||||
return CP_GET_SUCCESS;
|
||||
|
||||
/* Otherwise read the byte and return it */
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
*Byte = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_RECEIVER_BUFFER);
|
||||
else
|
||||
*Byte = READ_PORT_UCHAR((PUCHAR)SER1_IO_i_DATA);
|
||||
|
||||
/* TODO: Handle CD if port is in modem control mode */
|
||||
|
||||
/* Byte was read */
|
||||
return CP_GET_SUCCESS;
|
||||
}
|
||||
else if (IsNekoProject && Rs232ComPort[0].HasFifo)
|
||||
{
|
||||
/*
|
||||
* Neko Project 21/W doesn't set RxRDY without reading any data from 0x136.
|
||||
* TODO: Check real hardware behavior.
|
||||
*/
|
||||
(VOID)READ_PORT_UCHAR((PUCHAR)SER1_IO_i_INTERRUPT_ID);
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset LSR, no data was found */
|
||||
CpReadLsr(Port, 0);
|
||||
}
|
||||
else if (Port->Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
/* If "wait" mode enabled, spin many times, otherwise attempt just once */
|
||||
while (LimitCount--)
|
||||
{
|
||||
/* Read LSR for data ready */
|
||||
Lsr = CpReadLsr(Port, SER2_LSR_DR);
|
||||
if ((Lsr & SER2_LSR_DR) == SER2_LSR_DR)
|
||||
{
|
||||
/* If an error happened, clear the byte and fail */
|
||||
if (Lsr & (SER2_LSR_FE | SER2_LSR_PE | SER2_LSR_OE))
|
||||
{
|
||||
*Byte = 0;
|
||||
return CP_GET_ERROR;
|
||||
}
|
||||
|
||||
/* If only polling was requested by caller, return now */
|
||||
if (Poll)
|
||||
return CP_GET_SUCCESS;
|
||||
|
||||
/* Otherwise read the byte and return it */
|
||||
*Byte = READ_PORT_UCHAR((UCHAR)SER2_IO_i_RECEIVER_BUFFER);
|
||||
|
||||
/* TODO: Handle CD if port is in modem control mode */
|
||||
|
||||
/* Byte was read */
|
||||
return CP_GET_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset LSR, no data was found */
|
||||
CpReadLsr(Port, 0);
|
||||
}
|
||||
|
||||
return CP_GET_NODATA;
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
CpPutByte(
|
||||
IN PCPPORT Port,
|
||||
IN UCHAR Byte)
|
||||
{
|
||||
if (Port->Address == Rs232ComPort[0].Address)
|
||||
{
|
||||
/* TODO: Check if port is in modem control to handle CD */
|
||||
|
||||
if (Rs232ComPort[0].HasFifo)
|
||||
{
|
||||
while ((CpReadLsr(Port, SER1_LSR_TxRDY) & SER1_LSR_TxRDY) == 0)
|
||||
NOTHING;
|
||||
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_TRANSMITTER_BUFFER, Byte);
|
||||
}
|
||||
else
|
||||
{
|
||||
while ((CpReadLsr(Port, SER1_STATUS_TxRDY) & SER1_STATUS_TxRDY) == 0)
|
||||
NOTHING;
|
||||
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER1_IO_o_DATA, Byte);
|
||||
}
|
||||
}
|
||||
else if (Port->Address == Rs232ComPort[1].Address)
|
||||
{
|
||||
/* TODO: Check if port is in modem control to handle CD */
|
||||
|
||||
while ((CpReadLsr(Port, SER2_LSR_THR_EMPTY) & SER2_LSR_THR_EMPTY) == 0)
|
||||
NOTHING;
|
||||
|
||||
WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_TRANSMITTER_BUFFER, Byte);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue