mirror of https://github.com/reactos/reactos.git
[HALX86] Move PC/AT hardware definitions to a separate file (#2406)
This makes it easier for other ports.
This commit is contained in:
Dmitry Borisov
GitHub
parent
222e79232c
commit
18ae48ce51
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@ -59,6 +59,7 @@
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#include "bus.h"
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#include "halirq.h"
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#include "haldma.h"
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#include "halhw.h"
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#include "halp.h"
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#include "mps.h"
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#include "halacpi.h"
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@ -0,0 +1,376 @@
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/*
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* PROJECT: ReactOS Hardware Abstraction Layer
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: PC/AT hardware header file
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* COPYRIGHT: ...
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*/
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#pragma once
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/* CMOS Registers and Ports */
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#define CMOS_CONTROL_PORT (PUCHAR)0x70
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#define CMOS_DATA_PORT (PUCHAR)0x71
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#define RTC_REGISTER_A 0x0A
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#define RTC_REG_A_UIP 0x80
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#define RTC_REGISTER_B 0x0B
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#define RTC_REG_B_PI 0x40
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#define RTC_REGISTER_C 0x0C
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#define RTC_REG_C_IRQ 0x80
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#define RTC_REGISTER_D 0x0D
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#define RTC_REGISTER_CENTURY 0x32
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//
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// BIOS Interrupts
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//
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#define VIDEO_SERVICES 0x10
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//
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// Operations for INT 10h (in AH)
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//
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#define SET_VIDEO_MODE 0x00
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//
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// Video Modes for INT10h AH=00 (in AL)
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//
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#define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
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#if defined(SARCH_XBOX)
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//
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// For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
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// which is ~5.7% lower than on the PC.
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//
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#define PIT_FREQUENCY 1125000
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#else
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//
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// Commonly stated as being 1.19318MHz
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// p. 471
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//
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// However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
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// of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
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//
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// Note that Windows uses 1.193167MHz which seems to have no basis. However, if
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// one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
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// infinite series) and divides it by three, one obtains 1.19318167.
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//
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// It may be that the original NT HAL source code introduced a typo and turned
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// 119318167 into 1193167 by ommitting the "18". This is very plausible as the
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// number is quite long.
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//
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#define PIT_FREQUENCY 1193182
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#endif
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//
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// These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
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//
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#define TIMER_CHANNEL0_DATA_PORT 0x40
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#define TIMER_CHANNEL1_DATA_PORT 0x41
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#define TIMER_CHANNEL2_DATA_PORT 0x42
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#define TIMER_CONTROL_PORT 0x43
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//
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// Mode 0 - Interrupt On Terminal Count
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// Mode 1 - Hardware Re-triggerable One-Shot
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// Mode 2 - Rate Generator
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// Mode 3 - Square Wave Generator
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// Mode 4 - Software Triggered Strobe
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// Mode 5 - Hardware Triggered Strobe
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//
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typedef enum _TIMER_OPERATING_MODES
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{
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PitOperatingMode0,
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PitOperatingMode1,
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PitOperatingMode2,
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PitOperatingMode3,
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PitOperatingMode4,
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PitOperatingMode5,
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PitOperatingMode2Reserved,
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PitOperatingMode5Reserved
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} TIMER_OPERATING_MODES;
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typedef enum _TIMER_ACCESS_MODES
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{
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PitAccessModeCounterLatch,
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PitAccessModeLow,
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PitAccessModeHigh,
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PitAccessModeLowHigh
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} TIMER_ACCESS_MODES;
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typedef enum _TIMER_CHANNELS
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{
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PitChannel0,
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PitChannel1,
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PitChannel2,
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PitReadBack
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} TIMER_CHANNELS;
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typedef union _TIMER_CONTROL_PORT_REGISTER
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{
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struct
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{
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UCHAR BcdMode:1;
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UCHAR OperatingMode:3;
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UCHAR AccessMode:2;
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UCHAR Channel:2;
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};
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UCHAR Bits;
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} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 400
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//
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// This port is controled by the i8255 Programmable Peripheral Interface (PPI)
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//
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#define SYSTEM_CONTROL_PORT_A 0x92
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#define SYSTEM_CONTROL_PORT_B 0x61
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typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
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{
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struct
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{
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UCHAR Timer2GateToSpeaker:1;
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UCHAR SpeakerDataEnable:1;
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UCHAR ParityCheckEnable:1;
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UCHAR ChannelCheckEnable:1;
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UCHAR RefreshRequest:1;
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UCHAR Timer2Output:1;
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UCHAR ChannelCheck:1;
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UCHAR ParityCheck:1;
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};
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UCHAR Bits;
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} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
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//
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// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 396, 397
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//
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// These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
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//
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#define PIC1_CONTROL_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC2_CONTROL_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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//
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// Definitions for ICW/OCW Bits
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//
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typedef enum _I8259_ICW1_OPERATING_MODE
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{
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Cascade,
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Single
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} I8259_ICW1_OPERATING_MODE;
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typedef enum _I8259_ICW1_INTERRUPT_MODE
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{
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EdgeTriggered,
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LevelTriggered
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} I8259_ICW1_INTERRUPT_MODE;
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typedef enum _I8259_ICW1_INTERVAL
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{
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Interval8,
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Interval4
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} I8259_ICW1_INTERVAL;
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typedef enum _I8259_ICW4_SYSTEM_MODE
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{
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Mcs8085Mode,
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New8086Mode
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} I8259_ICW4_SYSTEM_MODE;
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typedef enum _I8259_ICW4_EOI_MODE
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{
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NormalEoi,
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AutomaticEoi
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} I8259_ICW4_EOI_MODE;
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typedef enum _I8259_ICW4_BUFFERED_MODE
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{
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NonBuffered,
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NonBuffered2,
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BufferedSlave,
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BufferedMaster
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} I8259_ICW4_BUFFERED_MODE;
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typedef enum _I8259_READ_REQUEST
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{
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InvalidRequest,
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InvalidRequest2,
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ReadIdr,
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ReadIsr
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} I8259_READ_REQUEST;
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typedef enum _I8259_EOI_MODE
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{
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RotateAutoEoiClear,
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NonSpecificEoi,
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InvalidEoiMode,
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SpecificEoi,
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RotateAutoEoiSet,
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RotateNonSpecific,
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SetPriority,
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RotateSpecific
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} I8259_EOI_MODE;
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//
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// Definitions for ICW Registers
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//
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typedef union _I8259_ICW1
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{
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struct
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{
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UCHAR NeedIcw4:1;
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UCHAR OperatingMode:1;
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UCHAR Interval:1;
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UCHAR InterruptMode:1;
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UCHAR Init:1;
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UCHAR InterruptVectorAddress:3;
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};
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UCHAR Bits;
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} I8259_ICW1, *PI8259_ICW1;
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typedef union _I8259_ICW2
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{
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struct
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{
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UCHAR Sbz:3;
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UCHAR InterruptVector:5;
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};
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UCHAR Bits;
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} I8259_ICW2, *PI8259_ICW2;
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typedef union _I8259_ICW3
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{
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union
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{
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struct
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{
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UCHAR SlaveIrq0:1;
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UCHAR SlaveIrq1:1;
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UCHAR SlaveIrq2:1;
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UCHAR SlaveIrq3:1;
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UCHAR SlaveIrq4:1;
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UCHAR SlaveIrq5:1;
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UCHAR SlaveIrq6:1;
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UCHAR SlaveIrq7:1;
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};
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struct
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{
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UCHAR SlaveId:3;
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UCHAR Reserved:5;
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};
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};
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UCHAR Bits;
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} I8259_ICW3, *PI8259_ICW3;
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typedef union _I8259_ICW4
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{
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struct
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{
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UCHAR SystemMode:1;
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UCHAR EoiMode:1;
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UCHAR BufferedMode:2;
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UCHAR SpecialFullyNestedMode:1;
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UCHAR Reserved:3;
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};
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UCHAR Bits;
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} I8259_ICW4, *PI8259_ICW4;
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typedef union _I8259_OCW2
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{
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struct
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{
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UCHAR IrqNumber:3;
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UCHAR Sbz:2;
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UCHAR EoiMode:3;
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};
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UCHAR Bits;
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} I8259_OCW2, *PI8259_OCW2;
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typedef union _I8259_OCW3
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{
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struct
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{
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UCHAR ReadRequest:2;
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UCHAR PollCommand:1;
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UCHAR Sbo:1;
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UCHAR Sbz:1;
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UCHAR SpecialMaskMode:2;
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UCHAR Reserved:1;
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};
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UCHAR Bits;
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} I8259_OCW3, *PI8259_OCW3;
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typedef union _I8259_ISR
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{
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union
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{
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struct
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{
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UCHAR Irq0:1;
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UCHAR Irq1:1;
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UCHAR Irq2:1;
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UCHAR Irq3:1;
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UCHAR Irq4:1;
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UCHAR Irq5:1;
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UCHAR Irq6:1;
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UCHAR Irq7:1;
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};
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};
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UCHAR Bits;
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} I8259_ISR, *PI8259_ISR;
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typedef I8259_ISR I8259_IDR, *PI8259_IDR;
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//
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// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
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// P. 34, 35
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//
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// These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
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//
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#define EISA_ELCR_MASTER 0x4D0
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#define EISA_ELCR_SLAVE 0x4D1
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typedef union _EISA_ELCR
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{
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struct
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{
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struct
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{
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UCHAR Irq0Level:1;
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UCHAR Irq1Level:1;
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UCHAR Irq2Level:1;
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UCHAR Irq3Level:1;
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UCHAR Irq4Level:1;
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UCHAR Irq5Level:1;
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UCHAR Irq6Level:1;
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UCHAR Irq7Level:1;
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} Master;
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struct
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{
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UCHAR Irq8Level:1;
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UCHAR Irq9Level:1;
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UCHAR Irq10Level:1;
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UCHAR Irq11Level:1;
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UCHAR Irq12Level:1;
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UCHAR Irq13Level:1;
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UCHAR Irq14Level:1;
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UCHAR Irq15Level:1;
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} Slave;
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};
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USHORT Bits;
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} EISA_ELCR, *PEISA_ELCR;
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typedef struct _PIC_MASK
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{
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union
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{
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struct
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{
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UCHAR Master;
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UCHAR Slave;
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};
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USHORT Both;
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};
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} PIC_MASK, *PPIC_MASK;
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@ -46,18 +46,6 @@ VOID
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#define HAL_PROFILING_INTERVAL 0
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#define HAL_PROFILING_MULTIPLIER 1
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/* CMOS Registers and Ports */
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#define CMOS_CONTROL_PORT (PUCHAR)0x70
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#define CMOS_DATA_PORT (PUCHAR)0x71
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#define RTC_REGISTER_A 0x0A
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#define RTC_REG_A_UIP 0x80
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#define RTC_REGISTER_B 0x0B
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#define RTC_REG_B_PI 0x40
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#define RTC_REGISTER_C 0x0C
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#define RTC_REG_C_IRQ 0x80
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#define RTC_REGISTER_D 0x0D
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#define RTC_REGISTER_CENTURY 0x32
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/* Usage flags */
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#define IDT_REGISTERED 0x01
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#define IDT_LATCHED 0x02
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@ -71,362 +59,6 @@ VOID
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#define INT_BCD(int) \
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(UCHAR)(((int / 10) << 4) + (int % 10))
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//
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// BIOS Interrupts
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//
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#define VIDEO_SERVICES 0x10
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|
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//
|
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// Operations for INT 10h (in AH)
|
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//
|
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#define SET_VIDEO_MODE 0x00
|
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|
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//
|
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// Video Modes for INT10h AH=00 (in AL)
|
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//
|
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#define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
|
||||
|
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#if defined(SARCH_XBOX)
|
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//
|
||||
// For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
|
||||
// which is ~5.7% lower than on the PC.
|
||||
//
|
||||
#define PIT_FREQUENCY 1125000
|
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#else
|
||||
//
|
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// Commonly stated as being 1.19318MHz
|
||||
//
|
||||
// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
|
||||
// p. 471
|
||||
//
|
||||
// However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
|
||||
// of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
|
||||
//
|
||||
// Note that Windows uses 1.193167MHz which seems to have no basis. However, if
|
||||
// one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
|
||||
// infinite series) and divides it by three, one obtains 1.19318167.
|
||||
//
|
||||
// It may be that the original NT HAL source code introduced a typo and turned
|
||||
// 119318167 into 1193167 by ommitting the "18". This is very plausible as the
|
||||
// number is quite long.
|
||||
//
|
||||
#define PIT_FREQUENCY 1193182
|
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#endif
|
||||
|
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//
|
||||
// These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
|
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//
|
||||
#define TIMER_CHANNEL0_DATA_PORT 0x40
|
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#define TIMER_CHANNEL1_DATA_PORT 0x41
|
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#define TIMER_CHANNEL2_DATA_PORT 0x42
|
||||
#define TIMER_CONTROL_PORT 0x43
|
||||
|
||||
//
|
||||
// Mode 0 - Interrupt On Terminal Count
|
||||
// Mode 1 - Hardware Re-triggerable One-Shot
|
||||
// Mode 2 - Rate Generator
|
||||
// Mode 3 - Square Wave Generator
|
||||
// Mode 4 - Software Triggered Strobe
|
||||
// Mode 5 - Hardware Triggered Strobe
|
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//
|
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typedef enum _TIMER_OPERATING_MODES
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{
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PitOperatingMode0,
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PitOperatingMode1,
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PitOperatingMode2,
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PitOperatingMode3,
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PitOperatingMode4,
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PitOperatingMode5,
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PitOperatingMode2Reserved,
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PitOperatingMode5Reserved
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} TIMER_OPERATING_MODES;
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typedef enum _TIMER_ACCESS_MODES
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{
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PitAccessModeCounterLatch,
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PitAccessModeLow,
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PitAccessModeHigh,
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PitAccessModeLowHigh
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} TIMER_ACCESS_MODES;
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typedef enum _TIMER_CHANNELS
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{
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PitChannel0,
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PitChannel1,
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PitChannel2,
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PitReadBack
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} TIMER_CHANNELS;
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typedef union _TIMER_CONTROL_PORT_REGISTER
|
||||
{
|
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struct
|
||||
{
|
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UCHAR BcdMode:1;
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UCHAR OperatingMode:3;
|
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UCHAR AccessMode:2;
|
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UCHAR Channel:2;
|
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};
|
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UCHAR Bits;
|
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} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
|
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|
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//
|
||||
// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
|
||||
// P. 400
|
||||
//
|
||||
// This port is controled by the i8255 Programmable Peripheral Interface (PPI)
|
||||
//
|
||||
#define SYSTEM_CONTROL_PORT_A 0x92
|
||||
#define SYSTEM_CONTROL_PORT_B 0x61
|
||||
typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Timer2GateToSpeaker:1;
|
||||
UCHAR SpeakerDataEnable:1;
|
||||
UCHAR ParityCheckEnable:1;
|
||||
UCHAR ChannelCheckEnable:1;
|
||||
UCHAR RefreshRequest:1;
|
||||
UCHAR Timer2Output:1;
|
||||
UCHAR ChannelCheck:1;
|
||||
UCHAR ParityCheck:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
|
||||
|
||||
//
|
||||
// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
|
||||
// P. 396, 397
|
||||
//
|
||||
// These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
|
||||
//
|
||||
#define PIC1_CONTROL_PORT 0x20
|
||||
#define PIC1_DATA_PORT 0x21
|
||||
#define PIC2_CONTROL_PORT 0xA0
|
||||
#define PIC2_DATA_PORT 0xA1
|
||||
|
||||
//
|
||||
// Definitions for ICW/OCW Bits
|
||||
//
|
||||
typedef enum _I8259_ICW1_OPERATING_MODE
|
||||
{
|
||||
Cascade,
|
||||
Single
|
||||
} I8259_ICW1_OPERATING_MODE;
|
||||
|
||||
typedef enum _I8259_ICW1_INTERRUPT_MODE
|
||||
{
|
||||
EdgeTriggered,
|
||||
LevelTriggered
|
||||
} I8259_ICW1_INTERRUPT_MODE;
|
||||
|
||||
typedef enum _I8259_ICW1_INTERVAL
|
||||
{
|
||||
Interval8,
|
||||
Interval4
|
||||
} I8259_ICW1_INTERVAL;
|
||||
|
||||
typedef enum _I8259_ICW4_SYSTEM_MODE
|
||||
{
|
||||
Mcs8085Mode,
|
||||
New8086Mode
|
||||
} I8259_ICW4_SYSTEM_MODE;
|
||||
|
||||
typedef enum _I8259_ICW4_EOI_MODE
|
||||
{
|
||||
NormalEoi,
|
||||
AutomaticEoi
|
||||
} I8259_ICW4_EOI_MODE;
|
||||
|
||||
typedef enum _I8259_ICW4_BUFFERED_MODE
|
||||
{
|
||||
NonBuffered,
|
||||
NonBuffered2,
|
||||
BufferedSlave,
|
||||
BufferedMaster
|
||||
} I8259_ICW4_BUFFERED_MODE;
|
||||
|
||||
typedef enum _I8259_READ_REQUEST
|
||||
{
|
||||
InvalidRequest,
|
||||
InvalidRequest2,
|
||||
ReadIdr,
|
||||
ReadIsr
|
||||
} I8259_READ_REQUEST;
|
||||
|
||||
typedef enum _I8259_EOI_MODE
|
||||
{
|
||||
RotateAutoEoiClear,
|
||||
NonSpecificEoi,
|
||||
InvalidEoiMode,
|
||||
SpecificEoi,
|
||||
RotateAutoEoiSet,
|
||||
RotateNonSpecific,
|
||||
SetPriority,
|
||||
RotateSpecific
|
||||
} I8259_EOI_MODE;
|
||||
|
||||
//
|
||||
// Definitions for ICW Registers
|
||||
//
|
||||
typedef union _I8259_ICW1
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR NeedIcw4:1;
|
||||
UCHAR OperatingMode:1;
|
||||
UCHAR Interval:1;
|
||||
UCHAR InterruptMode:1;
|
||||
UCHAR Init:1;
|
||||
UCHAR InterruptVectorAddress:3;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ICW1, *PI8259_ICW1;
|
||||
|
||||
typedef union _I8259_ICW2
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Sbz:3;
|
||||
UCHAR InterruptVector:5;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ICW2, *PI8259_ICW2;
|
||||
|
||||
typedef union _I8259_ICW3
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR SlaveIrq0:1;
|
||||
UCHAR SlaveIrq1:1;
|
||||
UCHAR SlaveIrq2:1;
|
||||
UCHAR SlaveIrq3:1;
|
||||
UCHAR SlaveIrq4:1;
|
||||
UCHAR SlaveIrq5:1;
|
||||
UCHAR SlaveIrq6:1;
|
||||
UCHAR SlaveIrq7:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
UCHAR SlaveId:3;
|
||||
UCHAR Reserved:5;
|
||||
};
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ICW3, *PI8259_ICW3;
|
||||
|
||||
typedef union _I8259_ICW4
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR SystemMode:1;
|
||||
UCHAR EoiMode:1;
|
||||
UCHAR BufferedMode:2;
|
||||
UCHAR SpecialFullyNestedMode:1;
|
||||
UCHAR Reserved:3;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ICW4, *PI8259_ICW4;
|
||||
|
||||
typedef union _I8259_OCW2
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR IrqNumber:3;
|
||||
UCHAR Sbz:2;
|
||||
UCHAR EoiMode:3;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_OCW2, *PI8259_OCW2;
|
||||
|
||||
typedef union _I8259_OCW3
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR ReadRequest:2;
|
||||
UCHAR PollCommand:1;
|
||||
UCHAR Sbo:1;
|
||||
UCHAR Sbz:1;
|
||||
UCHAR SpecialMaskMode:2;
|
||||
UCHAR Reserved:1;
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_OCW3, *PI8259_OCW3;
|
||||
|
||||
typedef union _I8259_ISR
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Irq0:1;
|
||||
UCHAR Irq1:1;
|
||||
UCHAR Irq2:1;
|
||||
UCHAR Irq3:1;
|
||||
UCHAR Irq4:1;
|
||||
UCHAR Irq5:1;
|
||||
UCHAR Irq6:1;
|
||||
UCHAR Irq7:1;
|
||||
};
|
||||
};
|
||||
UCHAR Bits;
|
||||
} I8259_ISR, *PI8259_ISR;
|
||||
|
||||
typedef I8259_ISR I8259_IDR, *PI8259_IDR;
|
||||
|
||||
//
|
||||
// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
|
||||
// P. 34, 35
|
||||
//
|
||||
// These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
|
||||
//
|
||||
#define EISA_ELCR_MASTER 0x4D0
|
||||
#define EISA_ELCR_SLAVE 0x4D1
|
||||
|
||||
typedef union _EISA_ELCR
|
||||
{
|
||||
struct
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Irq0Level:1;
|
||||
UCHAR Irq1Level:1;
|
||||
UCHAR Irq2Level:1;
|
||||
UCHAR Irq3Level:1;
|
||||
UCHAR Irq4Level:1;
|
||||
UCHAR Irq5Level:1;
|
||||
UCHAR Irq6Level:1;
|
||||
UCHAR Irq7Level:1;
|
||||
} Master;
|
||||
struct
|
||||
{
|
||||
UCHAR Irq8Level:1;
|
||||
UCHAR Irq9Level:1;
|
||||
UCHAR Irq10Level:1;
|
||||
UCHAR Irq11Level:1;
|
||||
UCHAR Irq12Level:1;
|
||||
UCHAR Irq13Level:1;
|
||||
UCHAR Irq14Level:1;
|
||||
UCHAR Irq15Level:1;
|
||||
} Slave;
|
||||
};
|
||||
USHORT Bits;
|
||||
} EISA_ELCR, *PEISA_ELCR;
|
||||
|
||||
typedef struct _PIC_MASK
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR Master;
|
||||
UCHAR Slave;
|
||||
};
|
||||
USHORT Both;
|
||||
};
|
||||
} PIC_MASK, *PPIC_MASK;
|
||||
|
||||
typedef
|
||||
BOOLEAN
|
||||
(NTAPI *PHAL_DISMISS_INTERRUPT)(
|
||||
|
|
|
|||
Loading…
Reference in New Issue