2010-04-01 19:07:40 +00:00
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/*
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* PROJECT: ReactOS PCI Bus Driver
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: drivers/bus/pci/utils.c
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* PURPOSE: Utility/Helper Support Code
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <pci.h>
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2014-01-04 12:05:02 +00:00
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2010-04-01 19:07:40 +00:00
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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2010-07-17 16:53:18 +00:00
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ULONG PciDebugPortsCount;
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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RTL_RANGE_LIST PciIsaBitExclusionList;
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RTL_RANGE_LIST PciVgaAndIsaBitExclusionList;
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2010-04-01 19:07:40 +00:00
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/* FUNCTIONS ******************************************************************/
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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BOOLEAN
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NTAPI
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PciUnicodeStringStrStr(IN PUNICODE_STRING InputString,
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IN PCUNICODE_STRING EqualString,
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IN BOOLEAN CaseInSensitive)
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{
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UNICODE_STRING PartialString;
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LONG EqualChars, TotalChars;
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/* Build a partial string with the smaller substring */
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PartialString.Length = EqualString->Length;
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2016-02-04 20:42:07 +00:00
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PartialString.MaximumLength = InputString->MaximumLength;
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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PartialString.Buffer = InputString->Buffer;
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/* Check how many characters that need comparing */
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EqualChars = 0;
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TotalChars = (InputString->Length - EqualString->Length) / sizeof(WCHAR);
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/* If the substring is bigger, just fail immediately */
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if (TotalChars < 0) return FALSE;
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/* Keep checking each character */
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while (!RtlEqualUnicodeString(EqualString, &PartialString, CaseInSensitive))
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{
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/* Continue checking until all the required characters are equal */
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PartialString.Buffer++;
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PartialString.MaximumLength -= sizeof(WCHAR);
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if (++EqualChars > TotalChars) return FALSE;
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}
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/* The string is equal */
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return TRUE;
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}
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BOOLEAN
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NTAPI
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PciStringToUSHORT(IN PWCHAR String,
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OUT PUSHORT Value)
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{
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USHORT Short;
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ULONG Low, High, Length;
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WCHAR Char;
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/* Initialize everything to zero */
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Short = 0;
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Length = 0;
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while (TRUE)
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{
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/* Get the character and set the high byte based on the previous one */
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Char = *String++;
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High = 16 * Short;
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/* Check for numbers */
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if ( Char >= '0' && Char <= '9' )
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{
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/* Convert them to a byte */
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Low = Char - '0';
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}
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else if ( Char >= 'A' && Char <= 'F' )
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{
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/* Convert upper-case hex letters into a byte */
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Low = Char - '7';
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}
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else if ( Char >= 'a' && Char <= 'f' )
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{
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/* Convert lower-case hex letters into a byte */
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Low = Char - 'W';
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}
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else
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{
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/* Invalid string, fail the conversion */
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return FALSE;
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}
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/* Combine the high and low byte */
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Short = High | Low;
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/* If 4 letters have been reached, the 16-bit integer should exist */
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if (++Length >= 4)
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{
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/* Return it to the caller */
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*Value = Short;
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return TRUE;
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}
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}
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}
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BOOLEAN
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NTAPI
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PciIsSuiteVersion(IN USHORT SuiteMask)
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{
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ULONGLONG Mask = 0;
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RTL_OSVERSIONINFOEXW VersionInfo;
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/* Initialize the version information */
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RtlZeroMemory(&VersionInfo, sizeof(RTL_OSVERSIONINFOEXW));
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VersionInfo.dwOSVersionInfoSize = sizeof(RTL_OSVERSIONINFOEXW);
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VersionInfo.wSuiteMask = SuiteMask;
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/* Set the comparison mask and return if the passed suite mask matches */
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VER_SET_CONDITION(Mask, VER_SUITENAME, VER_AND);
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return NT_SUCCESS(RtlVerifyVersionInfo(&VersionInfo, VER_SUITENAME, Mask));
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}
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BOOLEAN
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NTAPI
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PciIsDatacenter(VOID)
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{
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BOOLEAN Result;
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PVOID Value;
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ULONG ResultLength;
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NTSTATUS Status;
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/* Assume this isn't Datacenter */
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Result = FALSE;
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/* First, try opening the setup key */
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Status = PciGetRegistryValue(L"",
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L"\\REGISTRY\\MACHINE\\SYSTEM\\CurrentControlSet\\Services\\setupdd",
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0,
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REG_BINARY,
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&Value,
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&ResultLength);
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if (!NT_SUCCESS(Status))
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{
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/* This is not an in-progress Setup boot, so query the suite version */
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Result = PciIsSuiteVersion(VER_SUITE_DATACENTER);
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}
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else
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{
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/* This scenario shouldn't happen yet, since SetupDD isn't used */
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2013-01-10 01:49:15 +00:00
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UNIMPLEMENTED_FATAL("ReactOS doesn't use SetupDD for its installation program. Therefore this scenario must not happen!\n");
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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}
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/* Return if this is Datacenter or not */
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return Result;
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}
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BOOLEAN
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NTAPI
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PciOpenKey(IN PWCHAR KeyName,
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IN HANDLE RootKey,
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IN ACCESS_MASK DesiredAccess,
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OUT PHANDLE KeyHandle,
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OUT PNTSTATUS KeyStatus)
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{
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NTSTATUS Status;
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OBJECT_ATTRIBUTES ObjectAttributes;
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UNICODE_STRING KeyString;
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PAGED_CODE();
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/* Initialize the object attributes */
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RtlInitUnicodeString(&KeyString, KeyName);
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InitializeObjectAttributes(&ObjectAttributes,
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&KeyString,
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2022-05-04 14:23:54 +00:00
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OBJ_CASE_INSENSITIVE | OBJ_KERNEL_HANDLE,
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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RootKey,
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NULL);
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/* Open the key, returning a boolean, and the status, if requested */
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Status = ZwOpenKey(KeyHandle, DesiredAccess, &ObjectAttributes);
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if (KeyStatus) *KeyStatus = Status;
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return NT_SUCCESS(Status);
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}
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NTSTATUS
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NTAPI
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PciGetRegistryValue(IN PWCHAR ValueName,
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IN PWCHAR KeyName,
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IN HANDLE RootHandle,
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IN ULONG Type,
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OUT PVOID *OutputBuffer,
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OUT PULONG OutputLength)
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{
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NTSTATUS Status;
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PKEY_VALUE_PARTIAL_INFORMATION PartialInfo;
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ULONG NeededLength, ActualLength;
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UNICODE_STRING ValueString;
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HANDLE KeyHandle;
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BOOLEAN Result;
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/* So we know what to free at the end of the body */
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PartialInfo = NULL;
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KeyHandle = NULL;
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do
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{
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/* Open the key by name, rooted off the handle passed */
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Result = PciOpenKey(KeyName,
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RootHandle,
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KEY_QUERY_VALUE,
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&KeyHandle,
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&Status);
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if (!Result) break;
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/* Query for the size that's needed for the value that was passed in */
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RtlInitUnicodeString(&ValueString, ValueName);
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Status = ZwQueryValueKey(KeyHandle,
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&ValueString,
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KeyValuePartialInformation,
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NULL,
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0,
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&NeededLength);
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ASSERT(!NT_SUCCESS(Status));
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if (Status != STATUS_BUFFER_TOO_SMALL) break;
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/* Allocate an appropriate buffer for the size that was returned */
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ASSERT(NeededLength != 0);
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Status = STATUS_INSUFFICIENT_RESOURCES;
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PartialInfo = ExAllocatePoolWithTag(PagedPool,
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NeededLength,
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PCI_POOL_TAG);
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if (!PartialInfo) break;
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/* Query the actual value information now that the size is known */
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Status = ZwQueryValueKey(KeyHandle,
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&ValueString,
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KeyValuePartialInformation,
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PartialInfo,
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NeededLength,
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&ActualLength);
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if (!NT_SUCCESS(Status)) break;
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/* Make sure it's of the type that the caller expects */
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Status = STATUS_INVALID_PARAMETER;
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if (PartialInfo->Type != Type) break;
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/* Subtract the registry-specific header, to get the data size */
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ASSERT(NeededLength == ActualLength);
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NeededLength -= sizeof(KEY_VALUE_PARTIAL_INFORMATION);
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/* Allocate a buffer to hold the data and return it to the caller */
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Status = STATUS_INSUFFICIENT_RESOURCES;
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*OutputBuffer = ExAllocatePoolWithTag(PagedPool,
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NeededLength,
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PCI_POOL_TAG);
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if (!*OutputBuffer) break;
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/* Copy the data into the buffer and return its length to the caller */
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RtlCopyMemory(*OutputBuffer, PartialInfo->Data, NeededLength);
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if (OutputLength) *OutputLength = NeededLength;
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2010-06-29 20:21:45 +00:00
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Status = STATUS_SUCCESS;
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Begin implement full PCI Bus Driver. code by me comments by sir_richard to avoid Engrish
DriverEntry full 100% implemented, ACPI WatchDog detect, PCI IRQ Routing detect, PCI errata/hackflag detect (PciGetDebugPorts not support, need PCI Debug Device to test)
Native (S)ATA, PCI BIOS Resource Lock, System Errata/Hackflag also is detect
HAL Hoooking enabled, callbacks stub
Stub PnP Interfaces: PciAddDevice, PciDriverUnload, PciDispatchIrp
PCI utility routines: PciUnicodeStringStrStr, PciStringToUSHORT, PciIsSuiteVersion, PciIsDatacenter, PciOpenKey, PciGetRegistryValue, PciBuildDefaultExclusionList done
PCI Verifier Support for future: PciVerifierInit/PciVerifierProfileChangeCallback (stub)
Thank you for much patience~ This 1200 first codes, have 12000 codes more to come!~~
svn path=/trunk/; revision=47894
2010-06-28 05:23:31 +00:00
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} while (0);
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/* Close any opened keys and free temporary allocations */
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if (KeyHandle) ZwClose(KeyHandle);
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if (PartialInfo) ExFreePoolWithTag(PartialInfo, 0);
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return Status;
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}
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NTSTATUS
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NTAPI
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PciBuildDefaultExclusionLists(VOID)
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{
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ULONG Start;
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NTSTATUS Status;
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ASSERT(PciIsaBitExclusionList.Count == 0);
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ASSERT(PciVgaAndIsaBitExclusionList.Count == 0);
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/* Initialize the range lists */
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RtlInitializeRangeList(&PciIsaBitExclusionList);
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RtlInitializeRangeList(&PciVgaAndIsaBitExclusionList);
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/* Loop x86 I/O ranges */
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for (Start = 0x100; Start <= 0xFEFF; Start += 0x400)
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{
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/* Add the ISA I/O ranges */
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Status = RtlAddRange(&PciIsaBitExclusionList,
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Start,
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Start + 0x2FF,
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0,
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RTL_RANGE_LIST_ADD_IF_CONFLICT,
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NULL,
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NULL);
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if (!NT_SUCCESS(Status)) break;
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/* Add the ISA I/O ranges */
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Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
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Start,
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Start + 0x2AF,
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0,
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RTL_RANGE_LIST_ADD_IF_CONFLICT,
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NULL,
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NULL);
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if (!NT_SUCCESS(Status)) break;
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/* Add the VGA I/O range for Monochrome Video */
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Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
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Start + 0x2BC,
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Start + 0x2BF,
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0,
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RTL_RANGE_LIST_ADD_IF_CONFLICT,
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NULL,
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|
NULL);
|
|
|
|
if (!NT_SUCCESS(Status)) break;
|
|
|
|
|
|
|
|
/* Add the VGA I/O range for certain CGA adapters */
|
|
|
|
Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
|
|
|
|
Start + 0x2E0,
|
|
|
|
Start + 0x2FF,
|
|
|
|
0,
|
|
|
|
RTL_RANGE_LIST_ADD_IF_CONFLICT,
|
|
|
|
NULL,
|
|
|
|
NULL);
|
|
|
|
if (!NT_SUCCESS(Status)) break;
|
|
|
|
|
|
|
|
/* Success, ranges added done */
|
|
|
|
};
|
|
|
|
|
|
|
|
RtlFreeRangeList(&PciIsaBitExclusionList);
|
|
|
|
RtlFreeRangeList(&PciVgaAndIsaBitExclusionList);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
PPCI_FDO_EXTENSION
|
|
|
|
NTAPI
|
|
|
|
PciFindParentPciFdoExtension(IN PDEVICE_OBJECT DeviceObject,
|
|
|
|
IN PKEVENT Lock)
|
|
|
|
{
|
2010-07-17 15:09:19 +00:00
|
|
|
PPCI_FDO_EXTENSION DeviceExtension;
|
|
|
|
PPCI_PDO_EXTENSION SearchExtension, FoundExtension;
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
|
|
|
|
/* Assume we'll find nothing */
|
2010-07-17 15:09:19 +00:00
|
|
|
SearchExtension = DeviceObject->DeviceExtension;
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
FoundExtension = NULL;
|
|
|
|
|
|
|
|
/* Check if a lock was specified */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Wait for the lock to be released */
|
|
|
|
KeEnterCriticalRegion();
|
|
|
|
KeWaitForSingleObject(Lock, Executive, KernelMode, FALSE, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now search for the extension */
|
2010-07-17 15:09:19 +00:00
|
|
|
DeviceExtension = (PPCI_FDO_EXTENSION)PciFdoExtensionListHead.Next;
|
|
|
|
while (DeviceExtension)
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
{
|
2010-07-17 15:09:19 +00:00
|
|
|
/* Acquire this device's lock */
|
|
|
|
KeEnterCriticalRegion();
|
|
|
|
KeWaitForSingleObject(&DeviceExtension->ChildListLock,
|
|
|
|
Executive,
|
|
|
|
KernelMode,
|
|
|
|
FALSE,
|
|
|
|
NULL);
|
|
|
|
|
|
|
|
/* Scan all children PDO, stop when no more PDOs, or found it */
|
|
|
|
for (FoundExtension = DeviceExtension->ChildPdoList;
|
2010-09-23 13:24:41 +00:00
|
|
|
((FoundExtension) && (FoundExtension != SearchExtension));
|
2010-07-17 15:09:19 +00:00
|
|
|
FoundExtension = FoundExtension->Next);
|
|
|
|
|
|
|
|
/* Release this device's lock */
|
|
|
|
KeSetEvent(&DeviceExtension->ChildListLock, IO_NO_INCREMENT, FALSE);
|
|
|
|
KeLeaveCriticalRegion();
|
|
|
|
|
2010-09-23 13:24:41 +00:00
|
|
|
/* If we found it, break out */
|
|
|
|
if (FoundExtension) break;
|
|
|
|
|
2010-07-17 15:09:19 +00:00
|
|
|
/* Move to the next device */
|
|
|
|
DeviceExtension = (PPCI_FDO_EXTENSION)DeviceExtension->List.Next;
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if we had acquired a lock previously */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Release it */
|
|
|
|
KeSetEvent(Lock, IO_NO_INCREMENT, FALSE);
|
|
|
|
KeLeaveCriticalRegion();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return which extension was found, if any */
|
2010-07-17 15:09:19 +00:00
|
|
|
return DeviceExtension;
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
|
|
NTAPI
|
|
|
|
PciInsertEntryAtTail(IN PSINGLE_LIST_ENTRY ListHead,
|
|
|
|
IN PPCI_FDO_EXTENSION DeviceExtension,
|
|
|
|
IN PKEVENT Lock)
|
|
|
|
{
|
|
|
|
PSINGLE_LIST_ENTRY NextEntry;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Check if a lock was specified */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Wait for the lock to be released */
|
|
|
|
KeEnterCriticalRegion();
|
|
|
|
KeWaitForSingleObject(Lock, Executive, KernelMode, FALSE, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Loop the list until we get to the end, then insert this entry there */
|
|
|
|
for (NextEntry = ListHead; NextEntry->Next; NextEntry = NextEntry->Next);
|
|
|
|
NextEntry->Next = &DeviceExtension->List;
|
|
|
|
|
|
|
|
/* Check if we had acquired a lock previously */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Release it */
|
|
|
|
KeSetEvent(Lock, IO_NO_INCREMENT, FALSE);
|
|
|
|
KeLeaveCriticalRegion();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
|
|
NTAPI
|
|
|
|
PciInsertEntryAtHead(IN PSINGLE_LIST_ENTRY ListHead,
|
|
|
|
IN PSINGLE_LIST_ENTRY Entry,
|
|
|
|
IN PKEVENT Lock)
|
|
|
|
{
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Check if a lock was specified */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Wait for the lock to be released */
|
|
|
|
KeEnterCriticalRegion();
|
|
|
|
KeWaitForSingleObject(Lock, Executive, KernelMode, FALSE, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make the entry point to the current head and make the head point to it */
|
|
|
|
Entry->Next = ListHead->Next;
|
|
|
|
ListHead->Next = Entry;
|
|
|
|
|
|
|
|
/* Check if we had acquired a lock previously */
|
|
|
|
if (Lock)
|
|
|
|
{
|
|
|
|
/* Release it */
|
|
|
|
KeSetEvent(Lock, IO_NO_INCREMENT, FALSE);
|
|
|
|
KeLeaveCriticalRegion();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
|
|
NTAPI
|
|
|
|
PcipLinkSecondaryExtension(IN PSINGLE_LIST_ENTRY List,
|
|
|
|
IN PVOID Lock,
|
|
|
|
IN PPCI_SECONDARY_EXTENSION SecondaryExtension,
|
|
|
|
IN PCI_SIGNATURE ExtensionType,
|
|
|
|
IN PVOID Destructor)
|
|
|
|
{
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Setup the extension data, and insert it into the primary's list */
|
|
|
|
SecondaryExtension->ExtensionType = ExtensionType;
|
|
|
|
SecondaryExtension->Destructor = Destructor;
|
|
|
|
PciInsertEntryAtHead(List, &SecondaryExtension->List, Lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciGetDeviceProperty(IN PDEVICE_OBJECT DeviceObject,
|
|
|
|
IN DEVICE_REGISTRY_PROPERTY DeviceProperty,
|
|
|
|
OUT PVOID *OutputBuffer)
|
|
|
|
{
|
|
|
|
NTSTATUS Status;
|
|
|
|
ULONG BufferLength, ResultLength;
|
|
|
|
PVOID Buffer;
|
|
|
|
do
|
|
|
|
{
|
|
|
|
/* Query the requested property size */
|
|
|
|
Status = IoGetDeviceProperty(DeviceObject,
|
|
|
|
DeviceProperty,
|
|
|
|
0,
|
|
|
|
NULL,
|
|
|
|
&BufferLength);
|
|
|
|
if (Status != STATUS_BUFFER_TOO_SMALL)
|
|
|
|
{
|
|
|
|
/* Call should've failed with buffer too small! */
|
|
|
|
DPRINT1("PCI - Unexpected status from GetDeviceProperty, saw %08X, expected %08X.\n",
|
|
|
|
Status,
|
|
|
|
STATUS_BUFFER_TOO_SMALL);
|
|
|
|
*OutputBuffer = NULL;
|
2018-07-04 01:42:04 +00:00
|
|
|
ASSERTMSG("PCI Successfully did the impossible!\n", FALSE);
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate the required buffer */
|
|
|
|
Buffer = ExAllocatePoolWithTag(PagedPool, BufferLength, 'BicP');
|
|
|
|
if (!Buffer)
|
|
|
|
{
|
|
|
|
/* No memory, fail the request */
|
2013-05-10 10:22:01 +00:00
|
|
|
DPRINT1("PCI - Failed to allocate DeviceProperty buffer (%u bytes).\n", BufferLength);
|
Implement Root Bus FDO AddDevice codes, get boot config, connect to HAL or ACPI config handlers (PciQueryForPciBusInterface, PciGetConfigHandlers), read BUS FDO hack flag, get _HPP HotPlug PCI ACPI data and initialize arbiter support.
PciGetHotPlugParameters work but no PCI HotPlug support on my machines, so cannot test ACPI data, that part stub now
Add PciFdoDispatchTable, PciFdoDispatchPnpTable, PciFdoDispatchPowerTable but all stub to PciIrpNotSupported however set correct IRP Dispatch Style for the IRPS
Arbiter support in PciInitializeARbiters done, but PciInterfaces array is NULL (stub) at moment
Add PCI_SIGNATURE, PCI_STATE, PCI_DISAPTCH_STYLE type, add PciInitializeState to begin the state support
Add structure for PCI_FDO_EXTENSION, PCI_SECONDARY_EXTENSION, PCI_INTERFACE, PCI_ARBITER_INSTANCE, PCI_DISPATCH_TABLE
PCI utility functions added: PciFindParentPciFdoExtension, PciInsertEntryAtTail, PciInsertEntryAtHead, PcipLinkSecondaryExtension, PciGetDeviceProperty, PciSendIoctl
Need sir_richard to add arbiter.h header to define ARBITER_INSTANCE for finish support
This 1000 more codes done now~
svn path=/trunk/; revision=47898
2010-06-28 17:30:35 +00:00
|
|
|
Status = STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Do the actual property query call */
|
|
|
|
Status = IoGetDeviceProperty(DeviceObject,
|
|
|
|
DeviceProperty,
|
|
|
|
BufferLength,
|
|
|
|
Buffer,
|
|
|
|
&ResultLength);
|
|
|
|
if (!NT_SUCCESS(Status)) break;
|
|
|
|
|
|
|
|
/* Return the buffer to the caller */
|
|
|
|
ASSERT(BufferLength == ResultLength);
|
|
|
|
*OutputBuffer = Buffer;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
} while (FALSE);
|
|
|
|
|
|
|
|
/* Failure path */
|
|
|
|
return STATUS_UNSUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciSendIoctl(IN PDEVICE_OBJECT DeviceObject,
|
|
|
|
IN ULONG IoControlCode,
|
|
|
|
IN PVOID InputBuffer,
|
|
|
|
IN ULONG InputBufferLength,
|
|
|
|
IN PVOID OutputBuffer,
|
|
|
|
IN ULONG OutputBufferLength)
|
|
|
|
{
|
|
|
|
PIRP Irp;
|
|
|
|
NTSTATUS Status;
|
|
|
|
KEVENT Event;
|
|
|
|
IO_STATUS_BLOCK IoStatusBlock;
|
|
|
|
PDEVICE_OBJECT AttachedDevice;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Initialize the pending IRP event */
|
|
|
|
KeInitializeEvent(&Event, SynchronizationEvent, FALSE);
|
|
|
|
|
|
|
|
/* Get a reference to the root PDO (ACPI) */
|
|
|
|
AttachedDevice = IoGetAttachedDeviceReference(DeviceObject);
|
|
|
|
if (!AttachedDevice) return STATUS_INVALID_PARAMETER;
|
|
|
|
|
|
|
|
/* Build the requested IOCTL IRP */
|
|
|
|
Irp = IoBuildDeviceIoControlRequest(IoControlCode,
|
|
|
|
AttachedDevice,
|
|
|
|
InputBuffer,
|
|
|
|
InputBufferLength,
|
|
|
|
OutputBuffer,
|
|
|
|
OutputBufferLength,
|
|
|
|
0,
|
|
|
|
&Event,
|
|
|
|
&IoStatusBlock);
|
|
|
|
if (!Irp) return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
|
|
|
|
/* Send the IOCTL to the driver */
|
|
|
|
Status = IoCallDriver(AttachedDevice, Irp);
|
|
|
|
if (Status == STATUS_PENDING)
|
|
|
|
{
|
|
|
|
/* Wait for a response */
|
|
|
|
KeWaitForSingleObject(&Event,
|
|
|
|
Executive,
|
|
|
|
KernelMode,
|
|
|
|
FALSE,
|
|
|
|
NULL);
|
|
|
|
Status = Irp->IoStatus.Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Take away the reference we took and return the result to the caller */
|
|
|
|
ObDereferenceObject(AttachedDevice);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
2010-07-16 01:14:52 +00:00
|
|
|
PPCI_SECONDARY_EXTENSION
|
|
|
|
NTAPI
|
|
|
|
PciFindNextSecondaryExtension(IN PSINGLE_LIST_ENTRY ListHead,
|
|
|
|
IN PCI_SIGNATURE ExtensionType)
|
|
|
|
{
|
|
|
|
PSINGLE_LIST_ENTRY NextEntry;
|
|
|
|
PPCI_SECONDARY_EXTENSION Extension;
|
|
|
|
|
|
|
|
/* Scan the list */
|
|
|
|
for (NextEntry = ListHead; NextEntry; NextEntry = NextEntry->Next)
|
|
|
|
{
|
|
|
|
/* Grab each extension and check if it's the one requested */
|
|
|
|
Extension = CONTAINING_RECORD(NextEntry, PCI_SECONDARY_EXTENSION, List);
|
|
|
|
if (Extension->ExtensionType == ExtensionType) return Extension;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Nothing was found */
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2010-07-17 15:09:19 +00:00
|
|
|
ULONGLONG
|
|
|
|
NTAPI
|
|
|
|
PciGetHackFlags(IN USHORT VendorId,
|
|
|
|
IN USHORT DeviceId,
|
|
|
|
IN USHORT SubVendorId,
|
|
|
|
IN USHORT SubSystemId,
|
|
|
|
IN UCHAR RevisionId)
|
|
|
|
{
|
|
|
|
PPCI_HACK_ENTRY HackEntry;
|
|
|
|
ULONGLONG HackFlags;
|
|
|
|
ULONG LastWeight, MatchWeight;
|
|
|
|
ULONG EntryFlags;
|
2021-06-11 12:29:21 +00:00
|
|
|
|
2010-09-23 13:24:41 +00:00
|
|
|
/* ReactOS SetupLDR Hack */
|
|
|
|
if (!PciHackTable) return 0;
|
2010-07-17 15:09:19 +00:00
|
|
|
|
|
|
|
/* Initialize the variables before looping */
|
|
|
|
LastWeight = 0;
|
|
|
|
HackFlags = 0;
|
|
|
|
ASSERT(PciHackTable);
|
|
|
|
|
|
|
|
/* Scan the hack table */
|
|
|
|
for (HackEntry = PciHackTable;
|
|
|
|
HackEntry->VendorID != PCI_INVALID_VENDORID;
|
|
|
|
++HackEntry)
|
|
|
|
{
|
|
|
|
/* Check if there's an entry for this device */
|
|
|
|
if ((HackEntry->DeviceID == DeviceId) &&
|
|
|
|
(HackEntry->VendorID == VendorId))
|
|
|
|
{
|
|
|
|
/* This is a basic match */
|
|
|
|
EntryFlags = HackEntry->Flags;
|
|
|
|
MatchWeight = 1;
|
|
|
|
|
|
|
|
/* Does the entry have revision information? */
|
|
|
|
if (EntryFlags & PCI_HACK_HAS_REVISION_INFO)
|
|
|
|
{
|
|
|
|
/* Check if the revision matches, if so, this is a better match */
|
|
|
|
if (HackEntry->RevisionID != RevisionId) continue;
|
|
|
|
MatchWeight = 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Does the netry have subsystem information? */
|
|
|
|
if (EntryFlags & PCI_HACK_HAS_SUBSYSTEM_INFO)
|
|
|
|
{
|
|
|
|
/* Check if it matches, if so, this is the best possible match */
|
|
|
|
if ((HackEntry->SubVendorID != SubVendorId) ||
|
|
|
|
(HackEntry->SubSystemID != SubSystemId))
|
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
MatchWeight += 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Is this the best match yet? */
|
|
|
|
if (MatchWeight > LastWeight)
|
|
|
|
{
|
|
|
|
/* This is the best match for now, use this as the hack flags */
|
|
|
|
HackFlags = HackEntry->HackFlags;
|
|
|
|
LastWeight = MatchWeight;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the best match */
|
|
|
|
return HackFlags;
|
|
|
|
}
|
|
|
|
|
|
|
|
BOOLEAN
|
|
|
|
NTAPI
|
|
|
|
PciIsCriticalDeviceClass(IN UCHAR BaseClass,
|
|
|
|
IN UCHAR SubClass)
|
|
|
|
{
|
|
|
|
/* Check for system or bridge devices */
|
|
|
|
if (BaseClass == PCI_CLASS_BASE_SYSTEM_DEV)
|
|
|
|
{
|
2016-11-13 15:31:39 +00:00
|
|
|
/* Interrupt controllers are critical */
|
2010-07-17 15:09:19 +00:00
|
|
|
return SubClass == PCI_SUBCLASS_SYS_INTERRUPT_CTLR;
|
|
|
|
}
|
|
|
|
else if (BaseClass == PCI_CLASS_BRIDGE_DEV)
|
|
|
|
{
|
|
|
|
/* ISA Bridges are critical */
|
|
|
|
return SubClass == PCI_SUBCLASS_BR_ISA;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* All display controllers are critical */
|
|
|
|
return BaseClass == PCI_CLASS_DISPLAY_CTLR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
PPCI_PDO_EXTENSION
|
|
|
|
NTAPI
|
|
|
|
PciFindPdoByFunction(IN PPCI_FDO_EXTENSION DeviceExtension,
|
|
|
|
IN ULONG FunctionNumber,
|
|
|
|
IN PPCI_COMMON_HEADER PciData)
|
|
|
|
{
|
|
|
|
KIRQL Irql;
|
|
|
|
PPCI_PDO_EXTENSION PdoExtension;
|
|
|
|
|
|
|
|
/* Get the current IRQL when this call was made */
|
|
|
|
Irql = KeGetCurrentIrql();
|
|
|
|
|
|
|
|
/* Is this a low-IRQL call? */
|
|
|
|
if (Irql < DISPATCH_LEVEL)
|
|
|
|
{
|
|
|
|
/* Acquire this device's lock */
|
|
|
|
KeEnterCriticalRegion();
|
|
|
|
KeWaitForSingleObject(&DeviceExtension->ChildListLock,
|
|
|
|
Executive,
|
|
|
|
KernelMode,
|
|
|
|
FALSE,
|
|
|
|
NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Loop every child PDO */
|
|
|
|
for (PdoExtension = DeviceExtension->ChildPdoList;
|
|
|
|
PdoExtension;
|
|
|
|
PdoExtension = PdoExtension->Next)
|
|
|
|
{
|
|
|
|
/* Find only enumerated PDOs */
|
|
|
|
if (!PdoExtension->ReportedMissing)
|
|
|
|
{
|
|
|
|
/* Check if the function number and header data matches */
|
2010-07-17 15:59:09 +00:00
|
|
|
if ((FunctionNumber == PdoExtension->Slot.u.AsULONG) &&
|
2010-07-17 15:09:19 +00:00
|
|
|
(PdoExtension->VendorId == PciData->VendorID) &&
|
|
|
|
(PdoExtension->DeviceId == PciData->DeviceID) &&
|
|
|
|
(PdoExtension->RevisionId == PciData->RevisionID))
|
|
|
|
{
|
|
|
|
/* This is considered to be the same PDO */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Was this a low-IRQL call? */
|
|
|
|
if (Irql < DISPATCH_LEVEL)
|
|
|
|
{
|
|
|
|
/* Release this device's lock */
|
|
|
|
KeSetEvent(&DeviceExtension->ChildListLock, IO_NO_INCREMENT, FALSE);
|
|
|
|
KeLeaveCriticalRegion();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the search found something, this is non-NULL, otherwise it's NULL */
|
|
|
|
return PdoExtension;
|
|
|
|
}
|
|
|
|
|
2010-07-17 16:53:18 +00:00
|
|
|
BOOLEAN
|
|
|
|
NTAPI
|
|
|
|
PciIsDeviceOnDebugPath(IN PPCI_PDO_EXTENSION DeviceExtension)
|
|
|
|
{
|
|
|
|
PAGED_CODE();
|
|
|
|
|
2013-05-10 10:22:01 +00:00
|
|
|
UNREFERENCED_PARAMETER(DeviceExtension);
|
|
|
|
|
2010-07-17 16:53:18 +00:00
|
|
|
/* Check for too many, or no, debug ports */
|
|
|
|
ASSERT(PciDebugPortsCount <= MAX_DEBUGGING_DEVICES_SUPPORTED);
|
|
|
|
if (!PciDebugPortsCount) return FALSE;
|
|
|
|
|
|
|
|
/* eVb has not been able to test such devices yet */
|
2013-01-10 01:45:22 +00:00
|
|
|
UNIMPLEMENTED_DBGBREAK();
|
2013-01-04 11:47:19 +00:00
|
|
|
return FALSE;
|
2010-07-17 16:53:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciGetBiosConfig(IN PPCI_PDO_EXTENSION DeviceExtension,
|
|
|
|
OUT PPCI_COMMON_HEADER PciData)
|
|
|
|
{
|
|
|
|
HANDLE KeyHandle, SubKeyHandle;
|
|
|
|
OBJECT_ATTRIBUTES ObjectAttributes;
|
|
|
|
UNICODE_STRING KeyName, KeyValue;
|
|
|
|
WCHAR Buffer[32];
|
|
|
|
WCHAR DataBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) + PCI_COMMON_HDR_LENGTH];
|
|
|
|
PKEY_VALUE_PARTIAL_INFORMATION PartialInfo = (PVOID)DataBuffer;
|
|
|
|
NTSTATUS Status;
|
|
|
|
ULONG ResultLength;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Open the PCI key */
|
|
|
|
Status = IoOpenDeviceRegistryKey(DeviceExtension->ParentFdoExtension->
|
|
|
|
PhysicalDeviceObject,
|
|
|
|
TRUE,
|
|
|
|
KEY_ALL_ACCESS,
|
|
|
|
&KeyHandle);
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* Create a volatile BIOS configuration key */
|
|
|
|
RtlInitUnicodeString(&KeyName, L"BiosConfig");
|
|
|
|
InitializeObjectAttributes(&ObjectAttributes,
|
|
|
|
&KeyName,
|
|
|
|
OBJ_KERNEL_HANDLE,
|
|
|
|
KeyHandle,
|
|
|
|
NULL);
|
|
|
|
Status = ZwCreateKey(&SubKeyHandle,
|
|
|
|
KEY_READ,
|
|
|
|
&ObjectAttributes,
|
|
|
|
0,
|
|
|
|
NULL,
|
|
|
|
REG_OPTION_VOLATILE,
|
|
|
|
NULL);
|
|
|
|
ZwClose(KeyHandle);
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* Create the key value based on the device and function number */
|
|
|
|
swprintf(Buffer,
|
|
|
|
L"DEV_%02x&FUN_%02x",
|
|
|
|
DeviceExtension->Slot.u.bits.DeviceNumber,
|
|
|
|
DeviceExtension->Slot.u.bits.FunctionNumber);
|
|
|
|
RtlInitUnicodeString(&KeyValue, Buffer);
|
|
|
|
|
|
|
|
/* Query the value information (PCI BIOS configuration header) */
|
|
|
|
Status = ZwQueryValueKey(SubKeyHandle,
|
|
|
|
&KeyValue,
|
|
|
|
KeyValuePartialInformation,
|
|
|
|
PartialInfo,
|
|
|
|
sizeof(DataBuffer),
|
|
|
|
&ResultLength);
|
|
|
|
ZwClose(SubKeyHandle);
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* If any information was returned, go ahead and copy its data */
|
|
|
|
ASSERT(PartialInfo->DataLength == PCI_COMMON_HDR_LENGTH);
|
|
|
|
RtlCopyMemory(PciData, PartialInfo->Data, PCI_COMMON_HDR_LENGTH);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciSaveBiosConfig(IN PPCI_PDO_EXTENSION DeviceExtension,
|
|
|
|
IN PPCI_COMMON_HEADER PciData)
|
|
|
|
{
|
|
|
|
HANDLE KeyHandle, SubKeyHandle;
|
|
|
|
OBJECT_ATTRIBUTES ObjectAttributes;
|
|
|
|
UNICODE_STRING KeyName, KeyValue;
|
|
|
|
WCHAR Buffer[32];
|
|
|
|
NTSTATUS Status;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Open the PCI key */
|
|
|
|
Status = IoOpenDeviceRegistryKey(DeviceExtension->ParentFdoExtension->
|
|
|
|
PhysicalDeviceObject,
|
|
|
|
TRUE,
|
|
|
|
KEY_READ | KEY_WRITE,
|
|
|
|
&KeyHandle);
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* Create a volatile BIOS configuration key */
|
|
|
|
RtlInitUnicodeString(&KeyName, L"BiosConfig");
|
|
|
|
InitializeObjectAttributes(&ObjectAttributes,
|
|
|
|
&KeyName,
|
|
|
|
OBJ_KERNEL_HANDLE,
|
|
|
|
KeyHandle,
|
|
|
|
NULL);
|
|
|
|
Status = ZwCreateKey(&SubKeyHandle,
|
|
|
|
KEY_READ | KEY_WRITE,
|
|
|
|
&ObjectAttributes,
|
|
|
|
0,
|
|
|
|
NULL,
|
|
|
|
REG_OPTION_VOLATILE,
|
|
|
|
NULL);
|
|
|
|
ZwClose(KeyHandle);
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* Create the key value based on the device and function number */
|
|
|
|
swprintf(Buffer,
|
|
|
|
L"DEV_%02x&FUN_%02x",
|
|
|
|
DeviceExtension->Slot.u.bits.DeviceNumber,
|
|
|
|
DeviceExtension->Slot.u.bits.FunctionNumber);
|
|
|
|
RtlInitUnicodeString(&KeyValue, Buffer);
|
2010-07-18 18:58:33 +00:00
|
|
|
|
2010-07-17 16:53:18 +00:00
|
|
|
/* Set the value data (the PCI BIOS configuration header) */
|
|
|
|
Status = ZwSetValueKey(SubKeyHandle,
|
|
|
|
&KeyValue,
|
|
|
|
0,
|
|
|
|
REG_BINARY,
|
|
|
|
PciData,
|
|
|
|
PCI_COMMON_HDR_LENGTH);
|
|
|
|
ZwClose(SubKeyHandle);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
2010-07-18 18:58:33 +00:00
|
|
|
UCHAR
|
|
|
|
NTAPI
|
|
|
|
PciReadDeviceCapability(IN PPCI_PDO_EXTENSION DeviceExtension,
|
|
|
|
IN UCHAR Offset,
|
|
|
|
IN ULONG CapabilityId,
|
|
|
|
OUT PPCI_CAPABILITIES_HEADER Buffer,
|
|
|
|
IN ULONG Length)
|
|
|
|
{
|
|
|
|
ULONG CapabilityCount = 0;
|
|
|
|
|
|
|
|
/* If the device has no capabilility list, fail */
|
|
|
|
if (!Offset) return 0;
|
|
|
|
|
|
|
|
/* Validate a PDO with capabilities, a valid buffer, and a valid length */
|
|
|
|
ASSERT(DeviceExtension->ExtensionType == PciPdoExtensionType);
|
|
|
|
ASSERT(DeviceExtension->CapabilitiesPtr != 0);
|
|
|
|
ASSERT(Buffer);
|
|
|
|
ASSERT(Length >= sizeof(PCI_CAPABILITIES_HEADER));
|
|
|
|
|
|
|
|
/* Loop all capabilities */
|
|
|
|
while (Offset)
|
|
|
|
{
|
|
|
|
/* Make sure the pointer is spec-aligned and spec-sized */
|
|
|
|
ASSERT((Offset >= PCI_COMMON_HDR_LENGTH) && ((Offset & 0x3) == 0));
|
|
|
|
|
|
|
|
/* Read the capability header */
|
|
|
|
PciReadDeviceConfig(DeviceExtension,
|
|
|
|
Buffer,
|
|
|
|
Offset,
|
|
|
|
sizeof(PCI_CAPABILITIES_HEADER));
|
|
|
|
|
|
|
|
/* Check if this is the capability being looked up */
|
|
|
|
if ((Buffer->CapabilityID == CapabilityId) || !(CapabilityId))
|
|
|
|
{
|
|
|
|
/* Check if was at a valid offset and length */
|
|
|
|
if ((Offset) && (Length > sizeof(PCI_CAPABILITIES_HEADER)))
|
|
|
|
{
|
|
|
|
/* Sanity check */
|
|
|
|
ASSERT(Length <= (sizeof(PCI_COMMON_CONFIG) - Offset));
|
|
|
|
|
|
|
|
/* Now read the whole capability data into the buffer */
|
|
|
|
PciReadDeviceConfig(DeviceExtension,
|
|
|
|
(PVOID)((ULONG_PTR)Buffer +
|
|
|
|
sizeof(PCI_CAPABILITIES_HEADER)),
|
|
|
|
Offset + sizeof(PCI_CAPABILITIES_HEADER),
|
|
|
|
Length - sizeof(PCI_CAPABILITIES_HEADER));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the offset where the capability was found */
|
|
|
|
return Offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Try the next capability instead */
|
|
|
|
CapabilityCount++;
|
|
|
|
Offset = Buffer->Next;
|
|
|
|
|
|
|
|
/* There can't be more than 48 capabilities (256 bytes max) */
|
|
|
|
if (CapabilityCount > 48)
|
|
|
|
{
|
|
|
|
/* Fail, since this is basically a broken PCI device */
|
|
|
|
DPRINT1("PCI device %p capabilities list is broken.\n", DeviceExtension);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Capability wasn't found, fail */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
BOOLEAN
|
|
|
|
NTAPI
|
|
|
|
PciCanDisableDecodes(IN PPCI_PDO_EXTENSION DeviceExtension,
|
|
|
|
IN PPCI_COMMON_HEADER Config,
|
|
|
|
IN ULONGLONG HackFlags,
|
|
|
|
IN BOOLEAN ForPowerDown)
|
|
|
|
{
|
|
|
|
UCHAR BaseClass, SubClass;
|
|
|
|
BOOLEAN IsVga;
|
|
|
|
|
|
|
|
/* Is there a device extension or should the PCI header be used? */
|
|
|
|
if (DeviceExtension)
|
|
|
|
{
|
|
|
|
/* Never disable decodes for a debug PCI Device */
|
|
|
|
if (DeviceExtension->OnDebugPath) return FALSE;
|
|
|
|
|
|
|
|
/* Hack flags will be obtained from the extension, not the caller */
|
|
|
|
ASSERT(HackFlags == 0);
|
|
|
|
|
|
|
|
/* Get hacks and classification from the device extension */
|
|
|
|
HackFlags = DeviceExtension->HackFlags;
|
|
|
|
SubClass = DeviceExtension->SubClass;
|
|
|
|
BaseClass = DeviceExtension->BaseClass;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* There must be a PCI header, go read the classification information */
|
|
|
|
ASSERT(Config != NULL);
|
|
|
|
BaseClass = Config->BaseClass;
|
|
|
|
SubClass = Config->SubClass;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for hack flags that prevent disabling the decodes */
|
|
|
|
if (HackFlags & (PCI_HACK_PRESERVE_COMMAND |
|
|
|
|
PCI_HACK_CB_SHARE_CMD_BITS |
|
|
|
|
PCI_HACK_DONT_DISABLE_DECODES))
|
|
|
|
{
|
|
|
|
/* Don't do it */
|
|
|
|
return FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Is this a VGA adapter? */
|
|
|
|
if ((BaseClass == PCI_CLASS_DISPLAY_CTLR) &&
|
|
|
|
(SubClass == PCI_SUBCLASS_VID_VGA_CTLR))
|
|
|
|
{
|
|
|
|
/* Never disable decodes if this is for power down */
|
|
|
|
return ForPowerDown;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for legacy devices */
|
|
|
|
if (BaseClass == PCI_CLASS_PRE_20)
|
|
|
|
{
|
|
|
|
/* Never disable video adapter cards if this is for power down */
|
|
|
|
if (SubClass == PCI_SUBCLASS_PRE_20_VGA) return ForPowerDown;
|
|
|
|
}
|
|
|
|
else if (BaseClass == PCI_CLASS_DISPLAY_CTLR)
|
|
|
|
{
|
|
|
|
/* Never disable VGA adapters if this is for power down */
|
|
|
|
if (SubClass == PCI_SUBCLASS_VID_VGA_CTLR) return ForPowerDown;
|
|
|
|
}
|
|
|
|
else if (BaseClass == PCI_CLASS_BRIDGE_DEV)
|
|
|
|
{
|
|
|
|
/* Check for legacy bridges */
|
|
|
|
if ((SubClass == PCI_SUBCLASS_BR_ISA) ||
|
|
|
|
(SubClass == PCI_SUBCLASS_BR_EISA) ||
|
|
|
|
(SubClass == PCI_SUBCLASS_BR_MCA) ||
|
|
|
|
(SubClass == PCI_SUBCLASS_BR_HOST) ||
|
|
|
|
(SubClass == PCI_SUBCLASS_BR_OTHER))
|
|
|
|
{
|
|
|
|
/* Never disable these */
|
|
|
|
return FALSE;
|
|
|
|
}
|
|
|
|
else if ((SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) ||
|
|
|
|
(SubClass == PCI_SUBCLASS_BR_CARDBUS))
|
|
|
|
{
|
|
|
|
/* This is a supported bridge, but does it have a VGA card? */
|
|
|
|
if (!DeviceExtension)
|
|
|
|
{
|
|
|
|
/* Read the bridge control flag from the PCI header */
|
|
|
|
IsVga = Config->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Read the cached flag in the device extension */
|
|
|
|
IsVga = DeviceExtension->Dependent.type1.VgaBitSet;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Never disable VGA adapters if this is for power down */
|
|
|
|
if (IsVga) return ForPowerDown;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Finally, never disable decodes if there's no power management */
|
|
|
|
return !(HackFlags & PCI_HACK_NO_PM_CAPS);
|
|
|
|
}
|
|
|
|
|
2010-08-09 19:07:52 +00:00
|
|
|
PCI_DEVICE_TYPES
|
|
|
|
NTAPI
|
|
|
|
PciClassifyDeviceType(IN PPCI_PDO_EXTENSION PdoExtension)
|
|
|
|
{
|
|
|
|
ASSERT(PdoExtension->ExtensionType == PciPdoExtensionType);
|
|
|
|
|
2016-11-13 15:31:39 +00:00
|
|
|
/* Differentiate between devices and bridges */
|
2010-08-09 19:07:52 +00:00
|
|
|
if (PdoExtension->BaseClass != PCI_CLASS_BRIDGE_DEV) return PciTypeDevice;
|
|
|
|
|
|
|
|
/* The PCI Bus driver handles only CardBus and PCI bridges (plus host) */
|
|
|
|
if (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST) return PciTypeHostBridge;
|
|
|
|
if (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) return PciTypePciBridge;
|
|
|
|
if (PdoExtension->SubClass == PCI_SUBCLASS_BR_CARDBUS) return PciTypeCardbusBridge;
|
|
|
|
|
|
|
|
/* Any other kind of bridge is treated like a device */
|
|
|
|
return PciTypeDevice;
|
|
|
|
}
|
|
|
|
|
2010-07-19 16:35:52 +00:00
|
|
|
ULONG_PTR
|
|
|
|
NTAPI
|
|
|
|
PciExecuteCriticalSystemRoutine(IN ULONG_PTR IpiContext)
|
|
|
|
{
|
|
|
|
PPCI_IPI_CONTEXT Context = (PPCI_IPI_CONTEXT)IpiContext;
|
|
|
|
|
|
|
|
/* Check if the IPI is already running */
|
|
|
|
if (!InterlockedDecrement(&Context->RunCount))
|
|
|
|
{
|
|
|
|
/* Nope, this is the first instance, so execute the IPI function */
|
2010-09-12 06:03:12 +00:00
|
|
|
Context->Function(Context->DeviceExtension, Context->Context);
|
2010-07-19 16:35:52 +00:00
|
|
|
|
|
|
|
/* Notify anyone that was spinning that they can stop now */
|
|
|
|
Context->Barrier = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Spin until it has finished running */
|
|
|
|
while (Context->Barrier);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Done */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
Joint patch
By sir_richard: [PCIX]: - Implement PciIsSlotPresentInParentMethod for ACPI query, and PcoDecodeEnable utility function.
- Implement PciConfigureIdeController based on WDHC Whitepaper "How Windows Switches a Controller to Native Mode". Check for PciEanbleNativeModeATA in registry, InitSafeBootMode, and call the ACPI driver to evaluate if NATA is present on the slot. Only configure the controller if both channels support native mode, as this is a Windows restriction.
- Implement PciApplyHacks for enumeration and resource update cases. In the first case, we handle legacy DEC Alpha Intel i82375 and i82378 PCI-to-(E)ISA bridges with invalid class codes. In the second, we configure IDE controllers for Native mode, except the OPTi Viper-M, which is known to cause issues. We also support cards with legacy VGA decodes by telling the arbiter to enable full access to the rangesm and finally we completely disable the decodes on Compaq PCI Hotplug Controllers (Revision 17) on PAE systems, as they have bugs handling 64-bit addresses. Finally, on resource updates, we apply a vendor-specific errata to the IBM 20H2999 PCI Docking Bridge (Hotplug) used on Thinkpad 600 Series laptops, and we attempt to avoid issues that can happen on certain devices that are plugged into an ICH1/2/3/4 Intel Hub when it has been configured to do subtractive decode. Full information on these workarounds can be seen in the comments. Finally, we also enable CardBUS devices for ACPI-compliant mode, by crossing out the LegacyBaseAddress in the CardBUS Type 2 PCI Configuration Header.
- Miscelleaneous code cleanups.
By eVb: More PciScanBus support, for debug PCI caps that driver use are dump, and detect nonBIOS configure device (spec is said that CacheLineSize != 0, LatencyTimer != 0 (on PCI-X, != 64)), if found NeedsHotPlugConfiguration to be set
By eVb: Support PCI_HACK_VIDEO_LEGACY_DECODE (call ario_ApplyBrokenVideoHack, but no arb support to do work)
svn path=/trunk/; revision=48116
2010-07-19 15:15:39 +00:00
|
|
|
BOOLEAN
|
|
|
|
NTAPI
|
|
|
|
PciIsSlotPresentInParentMethod(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
IN ULONG Method)
|
|
|
|
{
|
|
|
|
BOOLEAN FoundSlot;
|
|
|
|
PACPI_METHOD_ARGUMENT Argument;
|
|
|
|
ACPI_EVAL_INPUT_BUFFER InputBuffer;
|
|
|
|
PACPI_EVAL_OUTPUT_BUFFER OutputBuffer;
|
|
|
|
ULONG i, Length;
|
|
|
|
NTSTATUS Status;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Assume slot is not part of the parent method */
|
|
|
|
FoundSlot = FALSE;
|
|
|
|
|
|
|
|
/* Allocate a 2KB buffer for the method return parameters */
|
|
|
|
Length = sizeof(ACPI_EVAL_OUTPUT_BUFFER) + 2048;
|
|
|
|
OutputBuffer = ExAllocatePoolWithTag(PagedPool, Length, 'BicP');
|
|
|
|
if (OutputBuffer)
|
|
|
|
{
|
|
|
|
/* Clear out the output buffer */
|
|
|
|
RtlZeroMemory(OutputBuffer, Length);
|
|
|
|
|
|
|
|
/* Initialize the input buffer with the method requested */
|
|
|
|
InputBuffer.Signature = 0;
|
|
|
|
*(PULONG)InputBuffer.MethodName = Method;
|
|
|
|
InputBuffer.Signature = ACPI_EVAL_INPUT_BUFFER_SIGNATURE;
|
|
|
|
|
|
|
|
/* Send it to the ACPI driver */
|
|
|
|
Status = PciSendIoctl(PdoExtension->ParentFdoExtension->PhysicalDeviceObject,
|
|
|
|
IOCTL_ACPI_EVAL_METHOD,
|
|
|
|
&InputBuffer,
|
|
|
|
sizeof(ACPI_EVAL_INPUT_BUFFER),
|
|
|
|
OutputBuffer,
|
|
|
|
Length);
|
|
|
|
if (NT_SUCCESS(Status))
|
|
|
|
{
|
|
|
|
/* Scan all output arguments */
|
|
|
|
for (i = 0; i < OutputBuffer->Count; i++)
|
|
|
|
{
|
|
|
|
/* Make sure it's an integer */
|
|
|
|
Argument = &OutputBuffer->Argument[i];
|
|
|
|
if (Argument->Type != ACPI_METHOD_ARGUMENT_INTEGER) continue;
|
|
|
|
|
|
|
|
/* Check if the argument matches this PCI slot structure */
|
|
|
|
if (Argument->Argument == ((PdoExtension->Slot.u.bits.DeviceNumber) |
|
|
|
|
((PdoExtension->Slot.u.bits.FunctionNumber) << 16)))
|
|
|
|
{
|
|
|
|
/* This slot has been found, return it */
|
|
|
|
FoundSlot = TRUE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Finished with the buffer, free it */
|
|
|
|
ExFreePoolWithTag(OutputBuffer, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return if the slot was found */
|
|
|
|
return FoundSlot;
|
|
|
|
}
|
|
|
|
|
Add all pci bridge control function (PciBridgeIoBase, PciBridgeIoLimit, PciBridgeMemoryBase, PciBridgeMemoryLimit, PciBridgePrefetchMemoryBase, PciBridgePrefetchMemoryLimit, PciBridgeMemoryWorstCasealignment, PciBridgeIsPositiveDecode, PciBridgeIsSubtractiveDecode)
More support ICH0/1/2/3/4 hub
Add all PCI2PCI bridge limit/current resource codes (PPBridge_*), now is BAR setup okay, and Device_* must be implement
Support ISA+VGA legacy decode, 20+64-bit decode, ROM BAR, prefetch BAR
svn path=/trunk/; revision=48298
2010-07-27 03:24:24 +00:00
|
|
|
ULONG
|
|
|
|
NTAPI
|
|
|
|
PciGetLengthFromBar(IN ULONG Bar)
|
|
|
|
{
|
|
|
|
ULONG Length;
|
|
|
|
|
|
|
|
/* I/O addresses vs. memory addresses start differently due to alignment */
|
|
|
|
Length = 1 << ((Bar & PCI_ADDRESS_IO_SPACE) ? 2 : 4);
|
|
|
|
|
|
|
|
/* Keep going until a set bit */
|
|
|
|
while (!(Length & Bar) && (Length)) Length <<= 1;
|
|
|
|
|
|
|
|
/* Return the length (might be 0 on 64-bit because it's the low-word) */
|
|
|
|
if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) != PCI_TYPE_64BIT) ASSERT(Length);
|
|
|
|
return Length;
|
|
|
|
}
|
|
|
|
|
|
|
|
BOOLEAN
|
|
|
|
NTAPI
|
|
|
|
PciCreateIoDescriptorFromBarLimit(PIO_RESOURCE_DESCRIPTOR ResourceDescriptor,
|
|
|
|
IN PULONG BarArray,
|
|
|
|
IN BOOLEAN Rom)
|
|
|
|
{
|
|
|
|
ULONG CurrentBar, BarLength, BarMask;
|
|
|
|
BOOLEAN Is64BitBar = FALSE;
|
|
|
|
|
|
|
|
/* Check if the BAR is nor I/O nor memory */
|
|
|
|
CurrentBar = BarArray[0];
|
|
|
|
if (!(CurrentBar & ~PCI_ADDRESS_IO_SPACE))
|
|
|
|
{
|
|
|
|
/* Fail this descriptor */
|
|
|
|
ResourceDescriptor->Type = CmResourceTypeNull;
|
|
|
|
return FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set default flag and clear high words */
|
|
|
|
ResourceDescriptor->Flags = 0;
|
|
|
|
ResourceDescriptor->u.Generic.MaximumAddress.HighPart = 0;
|
|
|
|
ResourceDescriptor->u.Generic.MinimumAddress.LowPart = 0;
|
|
|
|
ResourceDescriptor->u.Generic.MinimumAddress.HighPart = 0;
|
|
|
|
|
|
|
|
/* Check for ROM Address */
|
|
|
|
if (Rom)
|
|
|
|
{
|
|
|
|
/* Clean up the BAR to get just the address */
|
|
|
|
CurrentBar &= PCI_ADDRESS_ROM_ADDRESS_MASK;
|
|
|
|
if (!CurrentBar)
|
|
|
|
{
|
|
|
|
/* Invalid ar, fail this descriptor */
|
|
|
|
ResourceDescriptor->Type = CmResourceTypeNull;
|
|
|
|
return FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ROM Addresses are always read only */
|
|
|
|
ResourceDescriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Compute the length, assume it's the alignment for now */
|
|
|
|
BarLength = PciGetLengthFromBar(CurrentBar);
|
|
|
|
ResourceDescriptor->u.Generic.Length = BarLength;
|
|
|
|
ResourceDescriptor->u.Generic.Alignment = BarLength;
|
|
|
|
|
|
|
|
/* Check what kind of BAR this is */
|
|
|
|
if (CurrentBar & PCI_ADDRESS_IO_SPACE)
|
|
|
|
{
|
|
|
|
/* Use correct mask to decode the address */
|
|
|
|
BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
|
|
|
|
|
|
|
|
/* Set this as an I/O Port descriptor */
|
|
|
|
ResourceDescriptor->Type = CmResourceTypePort;
|
|
|
|
ResourceDescriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Use correct mask to decode the address */
|
|
|
|
BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
|
|
|
|
|
|
|
|
/* Set this as a memory descriptor */
|
|
|
|
ResourceDescriptor->Type = CmResourceTypeMemory;
|
|
|
|
|
|
|
|
/* Check if it's 64-bit or 20-bit decode */
|
|
|
|
if ((CurrentBar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
|
|
|
|
{
|
|
|
|
/* The next BAR has the high word, read it */
|
|
|
|
ResourceDescriptor->u.Port.MaximumAddress.HighPart = BarArray[1];
|
|
|
|
Is64BitBar = TRUE;
|
|
|
|
}
|
|
|
|
else if ((CurrentBar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
|
|
|
|
{
|
|
|
|
/* Use the correct mask to decode the address */
|
|
|
|
BarMask = ~0xFFF0000F;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if the BAR is listed as prefetchable memory */
|
|
|
|
if (CurrentBar & PCI_ADDRESS_MEMORY_PREFETCHABLE)
|
|
|
|
{
|
|
|
|
/* Mark the descriptor in the same way */
|
|
|
|
ResourceDescriptor->Flags |= CM_RESOURCE_MEMORY_PREFETCHABLE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now write down the maximum address based on the base + length */
|
|
|
|
ResourceDescriptor->u.Port.MaximumAddress.QuadPart = (CurrentBar & BarMask) +
|
|
|
|
BarLength - 1;
|
|
|
|
|
|
|
|
/* Return if this is a 64-bit BAR, so the loop code knows to skip the next one */
|
|
|
|
return Is64BitBar;
|
|
|
|
}
|
|
|
|
|
Joint patch
By sir_richard: [PCIX]: - Implement PciIsSlotPresentInParentMethod for ACPI query, and PcoDecodeEnable utility function.
- Implement PciConfigureIdeController based on WDHC Whitepaper "How Windows Switches a Controller to Native Mode". Check for PciEanbleNativeModeATA in registry, InitSafeBootMode, and call the ACPI driver to evaluate if NATA is present on the slot. Only configure the controller if both channels support native mode, as this is a Windows restriction.
- Implement PciApplyHacks for enumeration and resource update cases. In the first case, we handle legacy DEC Alpha Intel i82375 and i82378 PCI-to-(E)ISA bridges with invalid class codes. In the second, we configure IDE controllers for Native mode, except the OPTi Viper-M, which is known to cause issues. We also support cards with legacy VGA decodes by telling the arbiter to enable full access to the rangesm and finally we completely disable the decodes on Compaq PCI Hotplug Controllers (Revision 17) on PAE systems, as they have bugs handling 64-bit addresses. Finally, on resource updates, we apply a vendor-specific errata to the IBM 20H2999 PCI Docking Bridge (Hotplug) used on Thinkpad 600 Series laptops, and we attempt to avoid issues that can happen on certain devices that are plugged into an ICH1/2/3/4 Intel Hub when it has been configured to do subtractive decode. Full information on these workarounds can be seen in the comments. Finally, we also enable CardBUS devices for ACPI-compliant mode, by crossing out the LegacyBaseAddress in the CardBUS Type 2 PCI Configuration Header.
- Miscelleaneous code cleanups.
By eVb: More PciScanBus support, for debug PCI caps that driver use are dump, and detect nonBIOS configure device (spec is said that CacheLineSize != 0, LatencyTimer != 0 (on PCI-X, != 64)), if found NeedsHotPlugConfiguration to be set
By eVb: Support PCI_HACK_VIDEO_LEGACY_DECODE (call ario_ApplyBrokenVideoHack, but no arb support to do work)
svn path=/trunk/; revision=48116
2010-07-19 15:15:39 +00:00
|
|
|
VOID
|
|
|
|
NTAPI
|
|
|
|
PciDecodeEnable(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
IN BOOLEAN Enable,
|
|
|
|
OUT PUSHORT Command)
|
|
|
|
{
|
|
|
|
USHORT CommandValue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If decodes are being disabled, make sure it's allowed, and in both cases,
|
|
|
|
* make sure that a hackflag isn't preventing touching the decodes at all.
|
|
|
|
*/
|
|
|
|
if (((Enable) || (PciCanDisableDecodes(PdoExtension, 0, 0, 0))) &&
|
|
|
|
!(PdoExtension->HackFlags & PCI_HACK_PRESERVE_COMMAND))
|
|
|
|
{
|
|
|
|
/* Did the caller already have a command word? */
|
|
|
|
if (Command)
|
|
|
|
{
|
|
|
|
/* Use the caller's */
|
|
|
|
CommandValue = *Command;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Otherwise, read the current command */
|
|
|
|
PciReadDeviceConfig(PdoExtension,
|
|
|
|
&Command,
|
|
|
|
FIELD_OFFSET(PCI_COMMON_HEADER, Command),
|
|
|
|
sizeof(USHORT));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Turn off decodes by default */
|
|
|
|
CommandValue &= ~(PCI_ENABLE_IO_SPACE |
|
|
|
|
PCI_ENABLE_MEMORY_SPACE |
|
|
|
|
PCI_ENABLE_BUS_MASTER);
|
|
|
|
|
|
|
|
/* If requested, enable the decodes that were enabled at init time */
|
|
|
|
if (Enable) CommandValue |= PdoExtension->CommandEnables &
|
|
|
|
(PCI_ENABLE_IO_SPACE |
|
|
|
|
PCI_ENABLE_MEMORY_SPACE |
|
|
|
|
PCI_ENABLE_BUS_MASTER);
|
|
|
|
|
|
|
|
/* Update the command word */
|
|
|
|
PciWriteDeviceConfig(PdoExtension,
|
|
|
|
&CommandValue,
|
|
|
|
FIELD_OFFSET(PCI_COMMON_HEADER, Command),
|
|
|
|
sizeof(USHORT));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciQueryBusInformation(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
IN PPNP_BUS_INFORMATION* Buffer)
|
|
|
|
{
|
|
|
|
PPNP_BUS_INFORMATION BusInfo;
|
|
|
|
|
2013-05-10 10:22:01 +00:00
|
|
|
UNREFERENCED_PARAMETER(Buffer);
|
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Allocate a structure for the bus information */
|
|
|
|
BusInfo = ExAllocatePoolWithTag(PagedPool,
|
|
|
|
sizeof(PNP_BUS_INFORMATION),
|
|
|
|
'BicP');
|
|
|
|
if (!BusInfo) return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
|
|
|
|
/* Write the correct GUID and bus type identifier, and fill the bus number */
|
|
|
|
BusInfo->BusTypeGuid = GUID_BUS_TYPE_PCI;
|
|
|
|
BusInfo->LegacyBusType = PCIBus;
|
|
|
|
BusInfo->BusNumber = PdoExtension->ParentFdoExtension->BaseBus;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciDetermineSlotNumber(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
OUT PULONG SlotNumber)
|
|
|
|
{
|
|
|
|
PPCI_FDO_EXTENSION ParentExtension;
|
|
|
|
ULONG ResultLength;
|
|
|
|
NTSTATUS Status;
|
|
|
|
PSLOT_INFO SlotInfo;
|
|
|
|
|
|
|
|
/* Check if a $PIR from the BIOS is used (legacy IRQ routing) */
|
|
|
|
ParentExtension = PdoExtension->ParentFdoExtension;
|
2013-05-10 10:22:01 +00:00
|
|
|
DPRINT1("Slot lookup for %d.%u.%u\n",
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
ParentExtension ? ParentExtension->BaseBus : -1,
|
|
|
|
PdoExtension->Slot.u.bits.DeviceNumber,
|
|
|
|
PdoExtension->Slot.u.bits.FunctionNumber);
|
|
|
|
if ((PciIrqRoutingTable) && (ParentExtension))
|
|
|
|
{
|
|
|
|
/* Read every slot information entry */
|
|
|
|
SlotInfo = &PciIrqRoutingTable->Slot[0];
|
2013-05-10 10:22:01 +00:00
|
|
|
DPRINT1("PIR$ %p is %lx bytes, slot 0 is at: %p\n",
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
PciIrqRoutingTable, PciIrqRoutingTable->TableSize, SlotInfo);
|
|
|
|
while (SlotInfo < (PSLOT_INFO)((ULONG_PTR)PciIrqRoutingTable +
|
|
|
|
PciIrqRoutingTable->TableSize))
|
|
|
|
{
|
2013-05-10 10:22:01 +00:00
|
|
|
DPRINT1("Slot Info: %u.%u->#%u\n",
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
SlotInfo->BusNumber,
|
|
|
|
SlotInfo->DeviceNumber,
|
|
|
|
SlotInfo->SlotNumber);
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Check if this slot information matches the PDO being queried */
|
|
|
|
if ((ParentExtension->BaseBus == SlotInfo->BusNumber) &&
|
|
|
|
(PdoExtension->Slot.u.bits.DeviceNumber == SlotInfo->DeviceNumber >> 3) &&
|
|
|
|
(SlotInfo->SlotNumber))
|
|
|
|
{
|
|
|
|
/* We found it, return it and return success */
|
|
|
|
*SlotNumber = SlotInfo->SlotNumber;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Try the next slot */
|
|
|
|
SlotInfo++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise, grab the parent FDO and check if it's the root */
|
|
|
|
if (PCI_IS_ROOT_FDO(ParentExtension))
|
|
|
|
{
|
|
|
|
/* The root FDO doesn't have a slot number */
|
|
|
|
Status = STATUS_UNSUCCESSFUL;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Otherwise, query the slot/UI address/number as a device property */
|
|
|
|
Status = IoGetDeviceProperty(ParentExtension->PhysicalDeviceObject,
|
|
|
|
DevicePropertyUINumber,
|
|
|
|
sizeof(ULONG),
|
|
|
|
SlotNumber,
|
|
|
|
&ResultLength);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the status of this endeavour */
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciGetDeviceCapabilities(IN PDEVICE_OBJECT DeviceObject,
|
|
|
|
IN OUT PDEVICE_CAPABILITIES DeviceCapability)
|
|
|
|
{
|
|
|
|
PIRP Irp;
|
|
|
|
NTSTATUS Status;
|
|
|
|
KEVENT Event;
|
|
|
|
PDEVICE_OBJECT AttachedDevice;
|
|
|
|
PIO_STACK_LOCATION IoStackLocation;
|
|
|
|
IO_STATUS_BLOCK IoStatusBlock;
|
|
|
|
PAGED_CODE();
|
|
|
|
|
|
|
|
/* Zero out capabilities and set undefined values to start with */
|
|
|
|
RtlZeroMemory(DeviceCapability, sizeof(DEVICE_CAPABILITIES));
|
|
|
|
DeviceCapability->Size = sizeof(DEVICE_CAPABILITIES);
|
|
|
|
DeviceCapability->Version = 1;
|
|
|
|
DeviceCapability->Address = -1;
|
|
|
|
DeviceCapability->UINumber = -1;
|
|
|
|
|
|
|
|
/* Build the wait event for the IOCTL */
|
|
|
|
KeInitializeEvent(&Event, SynchronizationEvent, FALSE);
|
|
|
|
|
|
|
|
/* Find the device the PDO is attached to */
|
|
|
|
AttachedDevice = IoGetAttachedDeviceReference(DeviceObject);
|
|
|
|
|
|
|
|
/* And build an IRP for it */
|
|
|
|
Irp = IoBuildSynchronousFsdRequest(IRP_MJ_PNP,
|
|
|
|
AttachedDevice,
|
|
|
|
NULL,
|
|
|
|
0,
|
|
|
|
NULL,
|
|
|
|
&Event,
|
|
|
|
&IoStatusBlock);
|
|
|
|
if (!Irp)
|
|
|
|
{
|
|
|
|
/* The IRP failed, fail the request as well */
|
|
|
|
ObDereferenceObject(AttachedDevice);
|
|
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set default status */
|
|
|
|
Irp->IoStatus.Information = 0;
|
|
|
|
Irp->IoStatus.Status = STATUS_NOT_SUPPORTED;
|
|
|
|
|
|
|
|
/* Get a stack location in this IRP */
|
|
|
|
IoStackLocation = IoGetNextIrpStackLocation(Irp);
|
|
|
|
ASSERT(IoStackLocation);
|
|
|
|
|
|
|
|
/* Initialize it as a query capabilities IRP, with no completion routine */
|
|
|
|
RtlZeroMemory(IoStackLocation, sizeof(IO_STACK_LOCATION));
|
|
|
|
IoStackLocation->MajorFunction = IRP_MJ_PNP;
|
|
|
|
IoStackLocation->MinorFunction = IRP_MN_QUERY_CAPABILITIES;
|
|
|
|
IoStackLocation->Parameters.DeviceCapabilities.Capabilities = DeviceCapability;
|
|
|
|
IoSetCompletionRoutine(Irp, NULL, NULL, FALSE, FALSE, FALSE);
|
|
|
|
|
|
|
|
/* Send the IOCTL to the driver */
|
|
|
|
Status = IoCallDriver(AttachedDevice, Irp);
|
|
|
|
if (Status == STATUS_PENDING)
|
|
|
|
{
|
|
|
|
/* Wait for a response and update the actual status */
|
|
|
|
KeWaitForSingleObject(&Event,
|
|
|
|
Executive,
|
|
|
|
KernelMode,
|
|
|
|
FALSE,
|
|
|
|
NULL);
|
|
|
|
Status = Irp->IoStatus.Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Done, dereference the attached device and return the final result */
|
|
|
|
ObDereferenceObject(AttachedDevice);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciQueryPowerCapabilities(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
IN PDEVICE_CAPABILITIES DeviceCapability)
|
|
|
|
{
|
|
|
|
PDEVICE_OBJECT DeviceObject;
|
|
|
|
NTSTATUS Status;
|
|
|
|
DEVICE_CAPABILITIES AttachedCaps;
|
|
|
|
DEVICE_POWER_STATE NewPowerState, DevicePowerState, DeviceWakeLevel, DeviceWakeState;
|
|
|
|
SYSTEM_POWER_STATE SystemWakeState, DeepestWakeState, CurrentState;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Nothing is known at first */
|
|
|
|
DeviceWakeState = PowerDeviceUnspecified;
|
|
|
|
SystemWakeState = DeepestWakeState = PowerSystemUnspecified;
|
|
|
|
|
|
|
|
/* Get the PCI capabilities for the parent PDO */
|
|
|
|
DeviceObject = PdoExtension->ParentFdoExtension->PhysicalDeviceObject;
|
|
|
|
Status = PciGetDeviceCapabilities(DeviceObject, &AttachedCaps);
|
|
|
|
ASSERT(NT_SUCCESS(Status));
|
|
|
|
if (!NT_SUCCESS(Status)) return Status;
|
|
|
|
|
|
|
|
/* Check if there's not an existing device state for S0 */
|
|
|
|
if (!AttachedCaps.DeviceState[PowerSystemWorking])
|
|
|
|
{
|
|
|
|
/* Set D0<->S0 mapping */
|
|
|
|
AttachedCaps.DeviceState[PowerSystemWorking] = PowerDeviceD0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if there's not an existing device state for S3 */
|
|
|
|
if (!AttachedCaps.DeviceState[PowerSystemShutdown])
|
|
|
|
{
|
|
|
|
/* Set D3<->S3 mapping */
|
|
|
|
AttachedCaps.DeviceState[PowerSystemShutdown] = PowerDeviceD3;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for a PDO with broken, or no, power capabilities */
|
|
|
|
if (PdoExtension->HackFlags & PCI_HACK_NO_PM_CAPS)
|
|
|
|
{
|
|
|
|
/* Unknown wake device states */
|
|
|
|
DeviceCapability->DeviceWake = PowerDeviceUnspecified;
|
|
|
|
DeviceCapability->SystemWake = PowerSystemUnspecified;
|
|
|
|
|
|
|
|
/* No device state support */
|
|
|
|
DeviceCapability->DeviceD1 = FALSE;
|
|
|
|
DeviceCapability->DeviceD2 = FALSE;
|
|
|
|
|
|
|
|
/* No waking from any low-power device state is supported */
|
|
|
|
DeviceCapability->WakeFromD0 = FALSE;
|
|
|
|
DeviceCapability->WakeFromD1 = FALSE;
|
|
|
|
DeviceCapability->WakeFromD2 = FALSE;
|
|
|
|
DeviceCapability->WakeFromD3 = FALSE;
|
|
|
|
|
|
|
|
/* For the rest, copy whatever the parent PDO had */
|
|
|
|
RtlCopyMemory(DeviceCapability->DeviceState,
|
|
|
|
AttachedCaps.DeviceState,
|
|
|
|
sizeof(DeviceCapability->DeviceState));
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* The PCI Device has power capabilities, so read which ones are supported */
|
|
|
|
DeviceCapability->DeviceD1 = PdoExtension->PowerCapabilities.Support.D1;
|
|
|
|
DeviceCapability->DeviceD2 = PdoExtension->PowerCapabilities.Support.D2;
|
|
|
|
DeviceCapability->WakeFromD0 = PdoExtension->PowerCapabilities.Support.PMED0;
|
|
|
|
DeviceCapability->WakeFromD1 = PdoExtension->PowerCapabilities.Support.PMED1;
|
|
|
|
DeviceCapability->WakeFromD2 = PdoExtension->PowerCapabilities.Support.PMED2;
|
|
|
|
|
|
|
|
/* Can the attached device wake from D3? */
|
|
|
|
if (AttachedCaps.DeviceWake != PowerDeviceD3)
|
|
|
|
{
|
|
|
|
/* It can't, so check if this PDO supports hot D3 wake */
|
|
|
|
DeviceCapability->WakeFromD3 = PdoExtension->PowerCapabilities.Support.PMED3Hot;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* It can, is this the root bus? */
|
|
|
|
if (PCI_IS_ROOT_FDO(PdoExtension->ParentFdoExtension))
|
|
|
|
{
|
|
|
|
/* This is the root bus, so just check if it supports hot D3 wake */
|
|
|
|
DeviceCapability->WakeFromD3 = PdoExtension->PowerCapabilities.Support.PMED3Hot;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Take the minimums? -- need to check with briang at work */
|
|
|
|
UNIMPLEMENTED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now loop each system power state to determine its device state mapping */
|
|
|
|
for (CurrentState = PowerSystemWorking;
|
|
|
|
CurrentState < PowerSystemMaximum;
|
|
|
|
CurrentState++)
|
|
|
|
{
|
|
|
|
/* Read the current mapping from the attached device */
|
|
|
|
DevicePowerState = AttachedCaps.DeviceState[CurrentState];
|
|
|
|
NewPowerState = DevicePowerState;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
2016-11-13 15:31:39 +00:00
|
|
|
/* The attachee supports D1, but this PDO does not */
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
if ((NewPowerState == PowerDeviceD1) &&
|
|
|
|
!(PdoExtension->PowerCapabilities.Support.D1))
|
|
|
|
{
|
|
|
|
/* Fall back to D2 */
|
|
|
|
NewPowerState = PowerDeviceD2;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* The attachee supports D2, but this PDO does not */
|
|
|
|
if ((NewPowerState == PowerDeviceD2) &&
|
|
|
|
!(PdoExtension->PowerCapabilities.Support.D2))
|
|
|
|
{
|
|
|
|
/* Fall back to D3 */
|
|
|
|
NewPowerState = PowerDeviceD3;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Set the mapping based on the best state supported */
|
|
|
|
DeviceCapability->DeviceState[CurrentState] = NewPowerState;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Check if sleep states are being processed, and a mapping was found */
|
|
|
|
if ((CurrentState < PowerSystemHibernate) &&
|
|
|
|
(NewPowerState != PowerDeviceUnspecified))
|
|
|
|
{
|
|
|
|
/* Save this state as being the deepest one found until now */
|
|
|
|
DeepestWakeState = CurrentState;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
|
|
|
/*
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
* Finally, check if the computed sleep state is within the states that
|
|
|
|
* this device can wake the system from, and if it's higher or equal to
|
|
|
|
* the sleep state mapping that came from the attachee, assuming that it
|
|
|
|
* had a valid mapping to begin with.
|
|
|
|
*
|
|
|
|
* It this is the case, then make sure that the computed sleep state is
|
|
|
|
* matched by the device's ability to actually wake from that state.
|
|
|
|
*
|
|
|
|
* For devices that support D3, the PCI device only needs Hot D3 as long
|
|
|
|
* as the attachee's state is less than D3. Otherwise, if the attachee
|
|
|
|
* might also be at D3, this would require a Cold D3 wake, so check that
|
|
|
|
* the device actually support this.
|
|
|
|
*/
|
|
|
|
if ((CurrentState < AttachedCaps.SystemWake) &&
|
|
|
|
(NewPowerState >= DevicePowerState) &&
|
|
|
|
(DevicePowerState != PowerDeviceUnspecified) &&
|
|
|
|
(((NewPowerState == PowerDeviceD0) && (DeviceCapability->WakeFromD0)) ||
|
|
|
|
((NewPowerState == PowerDeviceD1) && (DeviceCapability->WakeFromD1)) ||
|
|
|
|
((NewPowerState == PowerDeviceD2) && (DeviceCapability->WakeFromD2)) ||
|
|
|
|
((NewPowerState == PowerDeviceD3) &&
|
|
|
|
(PdoExtension->PowerCapabilities.Support.PMED3Hot) &&
|
|
|
|
((DevicePowerState < PowerDeviceD3) ||
|
|
|
|
(PdoExtension->PowerCapabilities.Support.PMED3Cold)))))
|
|
|
|
{
|
|
|
|
/* The mapping is valid, so this will be the lowest wake state */
|
|
|
|
SystemWakeState = CurrentState;
|
|
|
|
DeviceWakeState = NewPowerState;
|
|
|
|
}
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Read the current wake level */
|
|
|
|
DeviceWakeLevel = PdoExtension->PowerState.DeviceWakeLevel;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Check if the attachee's wake levels are valid, and the PDO's is higher */
|
|
|
|
if ((AttachedCaps.SystemWake != PowerSystemUnspecified) &&
|
|
|
|
(AttachedCaps.DeviceWake != PowerDeviceUnspecified) &&
|
|
|
|
(DeviceWakeLevel != PowerDeviceUnspecified) &&
|
|
|
|
(DeviceWakeLevel >= AttachedCaps.DeviceWake))
|
|
|
|
{
|
|
|
|
/* Inherit the system wake from the attachee, and this PDO's wake level */
|
|
|
|
DeviceCapability->SystemWake = AttachedCaps.SystemWake;
|
|
|
|
DeviceCapability->DeviceWake = DeviceWakeLevel;
|
|
|
|
|
|
|
|
/* Now check if the wake level is D0, but the PDO doesn't support it */
|
|
|
|
if ((DeviceCapability->DeviceWake == PowerDeviceD0) &&
|
|
|
|
!(DeviceCapability->WakeFromD0))
|
|
|
|
{
|
|
|
|
/* Bump to D1 */
|
|
|
|
DeviceCapability->DeviceWake = PowerDeviceD1;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Now check if the wake level is D1, but the PDO doesn't support it */
|
|
|
|
if ((DeviceCapability->DeviceWake == PowerDeviceD1) &&
|
|
|
|
!(DeviceCapability->WakeFromD1))
|
|
|
|
{
|
|
|
|
/* Bump to D2 */
|
|
|
|
DeviceCapability->DeviceWake = PowerDeviceD2;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Now check if the wake level is D2, but the PDO doesn't support it */
|
|
|
|
if ((DeviceCapability->DeviceWake == PowerDeviceD2) &&
|
|
|
|
!(DeviceCapability->WakeFromD2))
|
|
|
|
{
|
|
|
|
/* Bump it to D3 */
|
|
|
|
DeviceCapability->DeviceWake = PowerDeviceD3;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Now check if the wake level is D3, but the PDO doesn't support it */
|
|
|
|
if ((DeviceCapability->DeviceWake == PowerDeviceD3) &&
|
|
|
|
!(DeviceCapability->WakeFromD3))
|
|
|
|
{
|
|
|
|
/* Then no valid wake state exists */
|
|
|
|
DeviceCapability->DeviceWake = PowerDeviceUnspecified;
|
|
|
|
DeviceCapability->SystemWake = PowerSystemUnspecified;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if no valid wake state was found */
|
|
|
|
if ((DeviceCapability->DeviceWake == PowerDeviceUnspecified) ||
|
|
|
|
(DeviceCapability->SystemWake == PowerSystemUnspecified))
|
|
|
|
{
|
|
|
|
/* Check if one was computed earlier */
|
|
|
|
if ((SystemWakeState != PowerSystemUnspecified) &&
|
|
|
|
(DeviceWakeState != PowerDeviceUnspecified))
|
|
|
|
{
|
|
|
|
/* Use the wake state that had been computed earlier */
|
|
|
|
DeviceCapability->DeviceWake = DeviceWakeState;
|
|
|
|
DeviceCapability->SystemWake = SystemWakeState;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* If that state was D3, then the device supports Hot/Cold D3 */
|
|
|
|
if (DeviceWakeState == PowerDeviceD3) DeviceCapability->WakeFromD3 = TRUE;
|
|
|
|
}
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/*
|
|
|
|
* Finally, check for off states (lower than S3, such as hibernate) and
|
|
|
|
* make sure that the device both supports waking from D3 as well as
|
|
|
|
* supports a Cold wake
|
|
|
|
*/
|
|
|
|
if ((DeviceCapability->SystemWake > PowerSystemSleeping3) &&
|
|
|
|
((DeviceCapability->DeviceWake != PowerDeviceD3) ||
|
|
|
|
!(PdoExtension->PowerCapabilities.Support.PMED3Cold)))
|
|
|
|
{
|
|
|
|
/* It doesn't, so pick the computed lowest wake state from earlier */
|
|
|
|
DeviceCapability->SystemWake = DeepestWakeState;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Set the PCI Specification mandated maximum latencies for transitions */
|
|
|
|
DeviceCapability->D1Latency = 0;
|
|
|
|
DeviceCapability->D2Latency = 2;
|
|
|
|
DeviceCapability->D3Latency = 100;
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* Sanity check */
|
|
|
|
ASSERT(DeviceCapability->DeviceState[PowerSystemWorking] == PowerDeviceD0);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* No valid sleep states, no latencies to worry about */
|
|
|
|
DeviceCapability->D1Latency = 0;
|
|
|
|
DeviceCapability->D2Latency = 0;
|
|
|
|
DeviceCapability->D3Latency = 0;
|
|
|
|
}
|
2010-08-14 17:33:10 +00:00
|
|
|
|
- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformation), IRP_MN_QUERY_ID (PciQueryId), IRP_MN_QUERY_DEVICE_TEXT (PciQueryDeviceText), IRP_MN_QUERY_CAPABILITIES (PciQueryCapabilities), IRP_MN_QUERY_DEVICE_RELATIONS (PciQueryTargetDeviceRelations implement, PciQueryEjectionRelations, stub)
- Stub support for PnP IRP to PDO: IRP_MN_QUERY_RESOURCE_REQUIREMENTS (PciQueryRequirements), IRP_MN_QUERY_RESOURCES(PciQueryResources)
- Add support for PnP IRP to FDO: IRP_MN_QUERY_CAPABILITIES (handle in PciFdoIrpQueryDeviceCapabilities)
- Build device capability UI number (PciDetermineSlotNumber), use PIR$ (seem support broken, need to check loader) or device property for bus not root
- Use parent attachee device and this PDO for build device/system wake states, latency, device/system power mappings
- PCI-ID manage support: PciInitIdBuffer, PciIdPrintf, PciIdPrintfAppend
- Debug helper: PciDebugDumpQueryCapabilities
- Thanks richard for advise + beer
PCI-X driver now pass 10000 codes lines!
svn path=/trunk/; revision=48548
2010-08-14 17:09:20 +00:00
|
|
|
/* This function always succeeds, even without power management support */
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
NTSTATUS
|
|
|
|
NTAPI
|
|
|
|
PciQueryCapabilities(IN PPCI_PDO_EXTENSION PdoExtension,
|
|
|
|
IN OUT PDEVICE_CAPABILITIES DeviceCapability)
|
|
|
|
{
|
|
|
|
NTSTATUS Status;
|
|
|
|
|
|
|
|
/* A PDO ID is never unique, and its address is its function and device */
|
|
|
|
DeviceCapability->UniqueID = FALSE;
|
|
|
|
DeviceCapability->Address = PdoExtension->Slot.u.bits.FunctionNumber |
|
|
|
|
(PdoExtension->Slot.u.bits.DeviceNumber << 16);
|
|
|
|
|
|
|
|
/* Check for host bridges */
|
|
|
|
if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
|
|
|
|
(PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST))
|
|
|
|
{
|
|
|
|
/* Raw device opens to a host bridge are acceptable */
|
|
|
|
DeviceCapability->RawDeviceOK = TRUE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Otherwise, other PDOs cannot be directly opened */
|
|
|
|
DeviceCapability->RawDeviceOK = FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI PDOs are pretty fixed things */
|
|
|
|
DeviceCapability->LockSupported = FALSE;
|
|
|
|
DeviceCapability->EjectSupported = FALSE;
|
|
|
|
DeviceCapability->Removable = FALSE;
|
|
|
|
DeviceCapability->DockDevice = FALSE;
|
|
|
|
|
|
|
|
/* The slot number is stored as a device property, go query it */
|
|
|
|
PciDetermineSlotNumber(PdoExtension, &DeviceCapability->UINumber);
|
|
|
|
|
|
|
|
/* Finally, query and power capabilities and convert them for PnP usage */
|
|
|
|
Status = PciQueryPowerCapabilities(PdoExtension, DeviceCapability);
|
|
|
|
|
|
|
|
/* Dump the capabilities if it all worked, and return the status */
|
|
|
|
if (NT_SUCCESS(Status)) PciDebugDumpQueryCapabilities(DeviceCapability);
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
2010-04-01 19:07:40 +00:00
|
|
|
/* EOF */
|