Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2024-07-18 02:16:14 +00:00
Code Issues Packages Projects Releases Wiki Activity
reactos/hal/halx86/apic/apictrap.S

47 lines
1 KiB
ArmAsm
Raw Normal View History

[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
/*
* FILE: hal/halx86/apic/apictrap.S
* COPYRIGHT: See COPYING in the top level directory
* PURPOSE: System Traps, Entrypoints and Exitpoints
* PROGRAMMER: Timo Kreuzer (timo.kreuzer@reactos.org)
* NOTE: See asmmacro.S for the shared entry/exit code.
*/
/* INCLUDES ******************************************************************/
#include <asm.inc>
#ifdef _M_AMD64
#include <ksamd64.inc>
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#include <trapamd64.inc>
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
.code
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
TRAP_ENTRY HalpClockInterrupt, (TF_VOLATILES OR TF_SEND_EOI)
TRAP_ENTRY HalpProfileInterrupt, (TF_VOLATILES OR TF_SEND_EOI)
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
PUBLIC ApicSpuriousService
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
ApicSpuriousService:
[HAL] Use iretq instead of iret
2020-02-02 08:45:17 +00:00
iretq
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
#else
#include <ks386.inc>
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#include <internal/i386/asmmacro.S>
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
.code
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
TRAP_ENTRY HalpClockInterrupt, KI_PUSH_FAKE_ERROR_CODE
TRAP_ENTRY HalpProfileInterrupt, KI_PUSH_FAKE_ERROR_CODE
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
TRAP_ENTRY HalpTrap0D, 0
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
TRAP_ENTRY HalpApcInterrupt, KI_PUSH_FAKE_ERROR_CODE
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
TRAP_ENTRY HalpDispatchInterrupt, KI_PUSH_FAKE_ERROR_CODE
[HAL] Add a hack to work around a bug in VBox: The APIC emulation requires an iret instruction following closely after writing the EOI register. Since we return from kernel mode traps with a jmp (yes you can return from an interrupt with a jmp!) the EOI is never triggered, making VBox believe we are still serving the interrupt and keeping the PPR on high level, preventing following interrupts. A small asm stub now does the work of both writing the EOI and doing an iret. svn path=/trunk/; revision=53665
2011-09-09 21:10:07 +00:00
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
PUBLIC _ApicSpuriousService
_ApicSpuriousService:
iret
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#endif
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
[HAL] Fix amd64 build svn path=/trunk/; revision=53704
2011-09-13 14:44:47 +00:00
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
END
Reference in a new issue Copy permalink