534 lines
9.5 KiB
C
534 lines
9.5 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "axp.h"
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typedef struct IOMap IOMap;
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struct IOMap
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{
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IOMap *next;
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char tag[13];
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ulong start;
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ulong end;
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};
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static struct
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{
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Lock;
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IOMap *m;
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IOMap *free;
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IOMap maps[32]; // some initial free maps
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QLock ql; // lock for reading map
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} iomap;
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enum {
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Qdir = 0,
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Qioalloc = 1,
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Qiob,
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Qiow,
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Qiol,
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Qbase,
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Qmax = 16,
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};
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typedef long Rdwrfn(Chan*, void*, long, vlong);
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static Rdwrfn *readfn[Qmax];
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static Rdwrfn *writefn[Qmax];
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static Dirtab archdir[] = {
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".", { Qdir, 0, QTDIR }, 0, 0555,
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"ioalloc", { Qioalloc, 0 }, 0, 0444,
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"iob", { Qiob, 0 }, 0, 0660,
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"iow", { Qiow, 0 }, 0, 0660,
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"iol", { Qiol, 0 }, 0, 0660,
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};
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Lock archwlock; /* the lock is only for changing archdir */
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int narchdir = Qbase;
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int (*_pcmspecial)(char *, ISAConf *);
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void (*_pcmspecialclose)(int);
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/*
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* Add a file to the #P listing. Once added, you can't delete it.
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* You can't add a file with the same name as one already there,
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* and you get a pointer to the Dirtab entry so you can do things
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* like change the Qid version. Changing the Qid path is disallowed.
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*/
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Dirtab*
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addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
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{
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int i;
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Dirtab d;
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Dirtab *dp;
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memset(&d, 0, sizeof d);
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strcpy(d.name, name);
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d.perm = perm;
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lock(&archwlock);
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if(narchdir >= Qmax){
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unlock(&archwlock);
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return nil;
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}
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for(i=0; i<narchdir; i++)
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if(strcmp(archdir[i].name, name) == 0){
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unlock(&archwlock);
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return nil;
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}
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d.qid.path = narchdir;
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archdir[narchdir] = d;
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readfn[narchdir] = rdfn;
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writefn[narchdir] = wrfn;
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dp = &archdir[narchdir++];
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unlock(&archwlock);
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return dp;
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}
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void
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ioinit(void)
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{
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int i;
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for(i = 0; i < nelem(iomap.maps)-1; i++)
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iomap.maps[i].next = &iomap.maps[i+1];
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iomap.maps[i].next = nil;
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iomap.free = iomap.maps;
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// a dummy entry at 2^17
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ioalloc(0x20000, 1, 0, "dummy");
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}
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//
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// alloc some io port space and remember who it was
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// alloced to. if port < 0, find a free region.
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//
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int
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ioalloc(int port, int size, int align, char *tag)
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{
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IOMap *m, **l;
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int i;
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lock(&iomap);
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if(port < 0){
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// find a free port above 0x400 and below 0x1000
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port = 0x400;
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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i = m->start - port;
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if(i > size)
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break;
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if(align > 0)
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port = ((port+align-1)/align)*align;
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else
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port = m->end;
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}
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if(*l == nil){
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unlock(&iomap);
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return -1;
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}
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} else {
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// see if the space clashes with previously allocated ports
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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if(m->end <= port)
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continue;
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if(m->start >= port+size)
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break;
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unlock(&iomap);
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return -1;
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}
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}
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m = iomap.free;
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if(m == nil){
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print("ioalloc: out of maps");
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unlock(&iomap);
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return port;
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}
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iomap.free = m->next;
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m->next = *l;
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m->start = port;
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m->end = port + size;
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strncpy(m->tag, tag, sizeof(m->tag));
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m->tag[sizeof(m->tag)-1] = 0;
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*l = m;
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archdir[0].qid.vers++;
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unlock(&iomap);
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return m->start;
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}
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void
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iofree(int port)
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{
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IOMap *m, **l;
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lock(&iomap);
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for(l = &iomap.m; *l; l = &(*l)->next){
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if((*l)->start == port){
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m = *l;
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*l = m->next;
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m->next = iomap.free;
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iomap.free = m;
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break;
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}
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if((*l)->start > port)
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break;
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}
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archdir[0].qid.vers++;
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unlock(&iomap);
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}
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int
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iounused(int start, int end)
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{
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IOMap *m;
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for(m = iomap.m; m; m = m->next){
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if(start >= m->start && start < m->end
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|| start <= m->start && end > m->start)
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return 0;
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}
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return 1;
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}
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static void
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checkport(int start, int end)
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{
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/* standard vga regs are OK */
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if(start >= 0x2b0 && end <= 0x2df+1)
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return;
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if(start >= 0x3c0 && end <= 0x3da+1)
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return;
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if(iounused(start, end))
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return;
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error(Eperm);
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}
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static Chan*
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archattach(char* spec)
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{
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return devattach('P', spec);
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}
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Walkqid*
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archwalk(Chan* c, Chan *nc, char** name, int nname)
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{
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return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
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}
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static int
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archstat(Chan* c, uchar* dp, int n)
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{
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return devstat(c, dp, n, archdir, narchdir, devgen);
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}
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static Chan*
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archopen(Chan* c, int omode)
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{
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return devopen(c, omode, archdir, nelem(archdir), devgen);
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}
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static void
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archclose(Chan*)
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{
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}
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enum
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{
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Linelen= 31,
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};
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static long
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archread(Chan *c, void *a, long n, vlong offset)
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{
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char buf[Linelen+1], *p;
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int port;
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ushort *sp;
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ulong *lp;
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IOMap *m;
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, archdir, nelem(archdir), devgen);
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case Qiob:
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port = offset;
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checkport(offset, offset+n);
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for(p = a; port < offset+n; port++)
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*p++ = inb(port);
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return n;
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case Qiow:
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if((n & 0x01) || (offset & 0x01))
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error(Ebadarg);
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checkport(offset, offset+n+1);
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n /= 2;
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sp = a;
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for(port = offset; port < offset+n; port += 2)
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*sp++ = ins(port);
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return n*2;
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case Qiol:
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if((n & 0x03) || (offset & 0x03))
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error(Ebadarg);
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checkport(offset, offset+n+3);
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n /= 4;
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lp = a;
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for(port = offset; port < offset+n; port += 4)
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*lp++ = inl(port);
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return n*4;
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case Qioalloc:
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break;
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default:
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if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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}
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offset = offset/Linelen;
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n = n/Linelen;
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p = a;
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lock(&iomap);
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for(m = iomap.m; n > 0 && m != nil; m = m->next){
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if(offset-- > 0)
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continue;
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if(strcmp(m->tag, "dummy") == 0)
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break;
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sprint(buf, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
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memmove(p, buf, Linelen);
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p += Linelen;
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n--;
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}
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unlock(&iomap);
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return p - (char*)a;
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}
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static long
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archwrite(Chan *c, void *a, long n, vlong offset)
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{
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char *p;
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int port;
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ushort *sp;
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ulong *lp;
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qiob:
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p = a;
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checkport(offset, offset+n);
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for(port = offset; port < offset+n; port++)
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outb(port, *p++);
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return n;
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case Qiow:
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if((n & 01) || (offset & 01))
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error(Ebadarg);
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checkport(offset, offset+n+1);
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n /= 2;
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sp = a;
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for(port = offset; port < offset+n; port += 2)
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outs(port, *sp++);
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return n*2;
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case Qiol:
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if((n & 0x03) || (offset & 0x03))
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error(Ebadarg);
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checkport(offset, offset+n+3);
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n /= 4;
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lp = a;
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for(port = offset; port < offset+n; port += 4)
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outl(port, *lp++);
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return n*4;
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default:
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if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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}
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return 0;
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}
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Dev archdevtab = {
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'P',
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"arch",
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devreset,
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devinit,
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devshutdown,
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archattach,
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archwalk,
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archstat,
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archopen,
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devcreate,
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archclose,
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archread,
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devbread,
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archwrite,
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devbwrite,
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devremove,
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devwstat,
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};
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PCArch* arch;
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extern PCArch* knownarch[];
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PCArch archgeneric = {
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"generic", /* id */
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0, /* ident */
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0, /* coreinit */
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0, /* coredetach */
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};
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static char *sysnames[] =
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{
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[1] "Alpha Demo. Unit",
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[2] "DEC 4000; Cobra",
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[3] "DEC 7000; Ruby",
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[4] "DEC 3000/500; Flamingo family (TC)",
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[6] "DEC 2000/300; Jensen (EISA/ISA)",
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[7] "DEC 3000/300; Pelican (TC)",
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[8] "Avalon A12; Avalon Multicomputer",
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[9] "DEC 2100/A500; Sable",
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[10] "DEC APXVME/64; AXPvme (VME?)",
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[11] "DEC AXPPCI/33; NoName (PCI/ISA)",
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[12] "DEC 21000; TurboLaser (PCI/EISA)",
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[13] "DEC 2100/A50; Avanti (PCI/ISA)",
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[14] "DEC MUSTANG; Mustang",
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[15] "DEC KN20AA; kn20aa (PCI/EISA)",
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[17] "DEC 1000; Mikasa (PCI/ISA?)",
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[19] "EB66; EB66 (PCI/ISA?)", // DEC?
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[20] "EB64P; EB64+ (PCI/ISA?)", // DEC?
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[21] "Alphabook1; Alphabook",
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[22] "DEC 4100; Rawhide (PCI/EISA)",
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[23] "DEC EV45/PBP; Lego",
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[24] "DEC 2100A/A500; Lynx",
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[26] "DEC AlphaPC 164", // only supported one: "EB164 (PCI/ISA)"
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[27] "DEC 1000A; Noritake",
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[28] "DEC AlphaVME/224; Cortex",
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[30] "DEC 550; Miata (PCI/ISA)",
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[32] "DEC EV56/PBP; Takara",
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[33] "DEC AlphaVME/320; Yukon (VME?)",
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[34] "DEC 6600; MonetGoldrush",
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// 200 and up is Alpha Processor Inc. machines
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// [201] "API UP1000; Nautilus",
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};
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static char *cpunames[] =
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{
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[1] "EV3",
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[2] "EV4: 21064",
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[3] "Simulation",
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[4] "LCA4: 2106[68]",
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[5] "EV5: 21164",
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[6] "EV45: 21064A",
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[7] "21164A", /* only supported one: EV56 */
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[8] "EV6: 21264",
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[9] "PCA256: 21164PC",
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};
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void
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cpuidprint(void)
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{
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int i, maj, min;
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Hwcpu *cpu;
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Hwdsr *dsr;
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char *s;
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print("\n");
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if (hwrpb->rev >= 6) {
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dsr = (Hwdsr*)((ulong)hwrpb + hwrpb->dsroff);
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s = (char*)dsr + dsr->sysnameoff + 8;
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print("%s\n", s);
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}
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else {
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s = "<unknown>";
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if (hwrpb->systype < nelem(sysnames))
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s = sysnames[hwrpb->systype];
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print("%s (%llux, %llux, %llux)\n", s, hwrpb->systype, hwrpb->sysvar, hwrpb->sysrev);
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}
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for (i = 0; i < hwrpb->ncpu; i++) {
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cpu = (Hwcpu*) ((ulong)hwrpb + hwrpb->cpuoff + i*hwrpb->cpulen);
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s = "<unknown>";
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maj = (ulong)cpu->cputype;
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min = (ulong)(cpu->cputype>>32);
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if (maj < nelem(cpunames))
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s = cpunames[maj];
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print("cpu%d: %s-%d (%d.%d, %llux, %llux)\n",
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i, s, min, maj, min, cpu->cpuvar, cpu->cpurev);
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}
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print("\n");
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}
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static long
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cputyperead(Chan*, void *a, long n, vlong offset)
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{
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char str[32], *cputype;
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ulong mhz, maj;
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Hwcpu *cpu;
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mhz = (m->cpuhz+999999)/1000000;
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cpu = (Hwcpu*) ((ulong)hwrpb + hwrpb->cpuoff); /* NB CPU 0 */
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cputype = "unknown";
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maj = (ulong)cpu->cputype;
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if (maj < nelem(cpunames))
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cputype = cpunames[maj];
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snprint(str, sizeof(str), "%s %lud\n", cputype, mhz);
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return readstr(offset, a, n, str);
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}
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void
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archinit(void)
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{
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PCArch **p;
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arch = 0;
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for(p = knownarch; *p; p++){
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if((*p)->ident && (*p)->ident() == 0){
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arch = *p;
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break;
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}
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}
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if(arch == 0)
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arch = &archgeneric;
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addarchfile("cputype", 0444, cputyperead, nil);
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}
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int
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pcmspecial(char *idstr, ISAConf *isa)
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{
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return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
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}
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void
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pcmspecialclose(int a)
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{
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if (_pcmspecialclose != nil)
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_pcmspecialclose(a);
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}
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