842 lines
20 KiB
C
842 lines
20 KiB
C
/*
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* Realtek 8139 (but not the 8129).
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* Error recovery for the various over/under -flow conditions
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* may need work.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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enum { /* registers */
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Idr0 = 0x0000, /* MAC address */
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Mar0 = 0x0008, /* Multicast address */
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Tsd0 = 0x0010, /* Transmit Status Descriptor0 */
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Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
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Rbstart = 0x0030, /* Receive Buffer Start Address */
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Erbcr = 0x0034, /* Early Receive Byte Count */
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Ersr = 0x0036, /* Early Receive Status */
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Cr = 0x0037, /* Command Register */
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Capr = 0x0038, /* Current Address of Packet Read */
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Cbr = 0x003A, /* Current Buffer Address */
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Imr = 0x003C, /* Interrupt Mask */
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Isr = 0x003E, /* Interrupt Status */
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Tcr = 0x0040, /* Transmit Configuration */
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Rcr = 0x0044, /* Receive Configuration */
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Tctr = 0x0048, /* Timer Count */
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Mpc = 0x004C, /* Missed Packet Counter */
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Cr9346 = 0x0050, /* 9346 Command Register */
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Config0 = 0x0051, /* Configuration Register 0 */
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Config1 = 0x0052, /* Configuration Register 1 */
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TimerInt = 0x0054, /* Timer Interrupt */
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Msr = 0x0058, /* Media Status */
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Config3 = 0x0059, /* Configuration Register 3 */
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Config4 = 0x005A, /* Configuration Register 4 */
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Mulint = 0x005C, /* Multiple Interrupt Select */
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RerID = 0x005E, /* PCI Revision ID */
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Tsad = 0x0060, /* Transmit Status of all Descriptors */
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Bmcr = 0x0062, /* Basic Mode Control */
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Bmsr = 0x0064, /* Basic Mode Status */
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Anar = 0x0066, /* Auto-Negotiation Advertisment */
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Anlpar = 0x0068, /* Auto-Negotiation Link Partner */
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Aner = 0x006A, /* Auto-Negotiation Expansion */
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Dis = 0x006C, /* Disconnect Counter */
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Fcsc = 0x006E, /* False Carrier Sense Counter */
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Nwaytr = 0x0070, /* N-way Test */
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Rec = 0x0072, /* RX_ER Counter */
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Cscr = 0x0074, /* CS Configuration */
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Phy1parm = 0x0078, /* PHY Parameter 1 */
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Twparm = 0x007C, /* Twister Parameter */
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Phy2parm = 0x0080, /* PHY Parameter 2 */
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};
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enum { /* Cr */
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Bufe = 0x01, /* Rx Buffer Empty */
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Te = 0x04, /* Transmitter Enable */
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Re = 0x08, /* Receiver Enable */
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Rst = 0x10, /* Software Reset */
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};
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enum { /* Imr/Isr */
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Rok = 0x0001, /* Receive OK */
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Rer = 0x0002, /* Receive Error */
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Tok = 0x0004, /* Transmit OK */
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Ter = 0x0008, /* Transmit Error */
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Rxovw = 0x0010, /* Receive Buffer Overflow */
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PunLc = 0x0020, /* Packet Underrun or Link Change */
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Fovw = 0x0040, /* Receive FIFO Overflow */
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Clc = 0x2000, /* Cable Length Change */
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Timerbit = 0x4000, /* Timer */
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Serr = 0x8000, /* System Error */
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};
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enum { /* Tcr */
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Clrabt = 0x00000001, /* Clear Abort */
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TxrrSHIFT = 4, /* Transmit Retry Count */
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TxrrMASK = 0x000000F0,
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MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
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MtxdmaMASK = 0x00000700,
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Mtxdma2048 = 0x00000700,
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Acrc = 0x00010000, /* Append CRC (not) */
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LbkSHIFT = 17, /* Loopback Test */
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LbkMASK = 0x00060000,
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Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */
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IfgSHIFT = 24, /* Interframe Gap */
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IfgMASK = 0x03000000,
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HwveridSHIFT = 26, /* Hardware Version ID */
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HwveridMASK = 0x7C000000,
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};
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enum { /* Rcr */
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Aap = 0x00000001, /* Accept All Packets */
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Apm = 0x00000002, /* Accept Physical Match */
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Am = 0x00000004, /* Accept Multicast */
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Ab = 0x00000008, /* Accept Broadcast */
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Ar = 0x00000010, /* Accept Runt */
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Aer = 0x00000020, /* Accept Error */
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Sel9356 = 0x00000040, /* 9356 EEPROM used */
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Wrap = 0x00000080, /* Rx Buffer Wrap Control */
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MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
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MrxdmaMASK = 0x00000700,
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Mrxdmaunlimited = 0x00000700,
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RblenSHIFT = 11, /* Receive Buffer Length */
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RblenMASK = 0x00001800,
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Rblen8K = 0x00000000, /* 8KB+16 */
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Rblen16K = 0x00000800, /* 16KB+16 */
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Rblen32K = 0x00001000, /* 32KB+16 */
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Rblen64K = 0x00001800, /* 64KB+16 */
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RxfthSHIFT = 13, /* Receive Buffer Length */
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RxfthMASK = 0x0000E000,
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Rxfth256 = 0x00008000,
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Rxfthnone = 0x0000E000,
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Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
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MulERINT = 0x00020000, /* Multiple Early Interrupt Select */
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ErxthSHIFT = 24, /* Early Rx Threshold */
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ErxthMASK = 0x0F000000,
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Erxthnone = 0x00000000,
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};
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enum { /* Received Packet Status */
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Rcok = 0x0001, /* Receive Completed OK */
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Fae = 0x0002, /* Frame Alignment Error */
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Crc = 0x0004, /* CRC Error */
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Long = 0x0008, /* Long Packet */
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Runt = 0x0010, /* Runt Packet Received */
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Ise = 0x0020, /* Invalid Symbol Error */
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Bar = 0x2000, /* Broadcast Address Received */
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Pam = 0x4000, /* Physical Address Matched */
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Mar = 0x8000, /* Multicast Address Received */
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};
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enum { /* Media Status Register */
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Rxpf = 0x01, /* Pause Flag */
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Txpf = 0x02, /* Pause Flag */
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Linkb = 0x04, /* Inverse of Link Status */
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Speed10 = 0x08, /* 10Mbps */
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Auxstatus = 0x10, /* Aux. Power Present Status */
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Rxfce = 0x40, /* Receive Flow Control Enable */
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Txfce = 0x80, /* Transmit Flow Control Enable */
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};
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typedef struct Td Td;
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struct Td { /* Soft Transmit Descriptor */
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int tsd;
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int tsad;
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uchar* data;
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Block* bp;
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};
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enum { /* Tsd0 */
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SizeSHIFT = 0, /* Descriptor Size */
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SizeMASK = 0x00001FFF,
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Own = 0x00002000,
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Tun = 0x00004000, /* Transmit FIFO Underrun */
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Tcok = 0x00008000, /* Transmit COmpleted OK */
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EtxthSHIFT = 16, /* Early Tx Threshold */
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EtxthMASK = 0x001F0000,
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NccSHIFT = 24, /* Number of Collisions Count */
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NccMASK = 0x0F000000,
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Cdh = 0x10000000, /* CD Heartbeat */
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Owc = 0x20000000, /* Out of Window Collision */
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Tabt = 0x40000000, /* Transmit Abort */
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Crs = 0x80000000, /* Carrier Sense Lost */
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};
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enum {
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Rblen = Rblen64K, /* Receive Buffer Length */
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Ntd = 4, /* Number of Transmit Descriptors */
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Tdbsz = ROUNDUP(sizeof(Etherpkt), 4),
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};
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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int id;
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QLock alock; /* attach */
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Lock ilock; /* init */
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void* alloc; /* base of per-Ctlr allocated data */
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int pcie; /* flag: pci-express device? */
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uvlong mchash; /* multicast hash */
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int rcr; /* receive configuration register */
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uchar* rbstart; /* receive buffer */
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int rblen; /* receive buffer length */
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int ierrs; /* receive errors */
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Lock tlock; /* transmit */
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Td td[Ntd];
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int ntd; /* descriptors active */
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int tdh; /* host index into td */
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int tdi; /* interface index into td */
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int etxth; /* early transmit threshold */
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int taligned; /* packet required no alignment */
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int tunaligned; /* packet required alignment */
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int dis; /* disconnect counter */
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int fcsc; /* false carrier sense counter */
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int rec; /* RX_ER counter */
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uint mcast;
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} Ctlr;
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static Ctlr* ctlrhead;
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static Ctlr* ctlrtail;
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#define csr8r(c, r) (inb((c)->port+(r)))
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#define csr16r(c, r) (ins((c)->port+(r)))
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#define csr32r(c, r) (inl((c)->port+(r)))
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#define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
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#define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
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#define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
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static void
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rtl8139promiscuous(void* arg, int on)
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{
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Ether *edev;
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Ctlr * ctlr;
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edev = arg;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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if(on)
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ctlr->rcr |= Aap;
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else
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ctlr->rcr &= ~Aap;
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csr32w(ctlr, Rcr, ctlr->rcr);
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iunlock(&ctlr->ilock);
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}
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enum {
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/* everyone else uses 0x04c11db7, but they both produce the same crc */
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Etherpolybe = 0x04c11db6,
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Bytemask = (1<<8) - 1,
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};
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static ulong
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ethercrcbe(uchar *addr, long len)
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{
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int i, j;
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ulong c, crc, carry;
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crc = ~0UL;
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for (i = 0; i < len; i++) {
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c = addr[i];
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for (j = 0; j < 8; j++) {
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carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
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crc <<= 1;
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c >>= 1;
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if (carry)
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crc = (crc ^ Etherpolybe) | carry;
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}
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}
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return crc;
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}
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static ulong
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swabl(ulong l)
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{
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return l>>24 | (l>>8) & (Bytemask<<8) |
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(l<<8) & (Bytemask<<16) | l<<24;
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}
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static void
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rtl8139multicast(void* ether, uchar *eaddr, int add)
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{
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Ether *edev;
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Ctlr *ctlr;
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if (!add)
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return; /* ok to keep receiving on old mcast addrs */
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edev = ether;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
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ctlr->rcr |= Am;
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csr32w(ctlr, Rcr, ctlr->rcr);
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/* pci-e variants reverse the order of the hash byte registers */
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if (0 && ctlr->pcie) {
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csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
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csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
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} else {
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csr32w(ctlr, Mar0, ctlr->mchash);
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csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
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}
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iunlock(&ctlr->ilock);
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}
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static long
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rtl8139ifstat(Ether* edev, void* a, long n, ulong offset)
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{
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int l;
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char *p;
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Ctlr *ctlr;
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ctlr = edev->ctlr;
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p = smalloc(READSTR);
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l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
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l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
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l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
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l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
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l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
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l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
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ctlr->dis += csr16r(ctlr, Dis);
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l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
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ctlr->fcsc += csr16r(ctlr, Fcsc);
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l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
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ctlr->rec += csr16r(ctlr, Rec);
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l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
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l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
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l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
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l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
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l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
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l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
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l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
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l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
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l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
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l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
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l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
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l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
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l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
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snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
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n = readstr(offset, a, n, p);
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free(p);
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return n;
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}
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static int
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rtl8139reset(Ctlr* ctlr)
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{
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int timeo;
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/*
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* Soft reset the controller.
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*/
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csr8w(ctlr, Cr, Rst);
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for(timeo = 0; timeo < 1000; timeo++){
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if(!(csr8r(ctlr, Cr) & Rst))
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return 0;
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delay(1);
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}
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return -1;
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}
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static void
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rtl8139halt(Ctlr* ctlr)
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{
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int i;
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csr8w(ctlr, Cr, 0);
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csr16w(ctlr, Imr, 0);
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csr16w(ctlr, Isr, ~0);
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for(i = 0; i < Ntd; i++){
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if(ctlr->td[i].bp == nil)
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continue;
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freeb(ctlr->td[i].bp);
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ctlr->td[i].bp = nil;
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}
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}
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static void
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rtl8139init(Ether* edev)
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{
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int i;
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ulong r;
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Ctlr *ctlr;
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uchar *alloc;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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rtl8139halt(ctlr);
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/*
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* MAC Address.
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*/
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r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
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csr32w(ctlr, Idr0, r);
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r = (edev->ea[5]<<8)|edev->ea[4];
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csr32w(ctlr, Idr0+4, r);
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/*
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* Receiver
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*/
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alloc = ctlr->alloc;
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ctlr->rbstart = alloc;
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alloc += ctlr->rblen+16;
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memset(ctlr->rbstart, 0, ctlr->rblen+16);
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csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
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ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
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/*
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* Transmitter.
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*/
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for(i = 0; i < Ntd; i++){
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ctlr->td[i].tsd = Tsd0+i*4;
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ctlr->td[i].tsad = Tsad0+i*4;
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ctlr->td[i].data = alloc;
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alloc += Tdbsz;
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ctlr->td[i].bp = nil;
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}
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ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
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ctlr->etxth = 128/32;
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/*
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* Interrupts.
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*/
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csr32w(ctlr, TimerInt, 0);
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csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
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csr32w(ctlr, Mpc, 0);
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/*
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* Enable receiver/transmitter.
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* Need to enable before writing the Rcr or it won't take.
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*/
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csr8w(ctlr, Cr, Te|Re);
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csr32w(ctlr, Tcr, Mtxdma2048);
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csr32w(ctlr, Rcr, ctlr->rcr);
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csr32w(ctlr, Mar0, 0);
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csr32w(ctlr, Mar0+4, 0);
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ctlr->mchash = 0;
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iunlock(&ctlr->ilock);
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}
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static void
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rtl8139attach(Ether* edev)
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{
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Ctlr *ctlr;
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ctlr = edev->ctlr;
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qlock(&ctlr->alock);
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if(ctlr->alloc == nil){
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ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
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ctlr->alloc = mallocalign(ctlr->rblen+16 + Ntd*Tdbsz, 32, 0, 0);
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if(ctlr->alloc == nil){
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qunlock(&ctlr->alock);
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error(Enomem);
|
|
}
|
|
rtl8139init(edev);
|
|
}
|
|
qunlock(&ctlr->alock);
|
|
}
|
|
|
|
static void
|
|
rtl8139txstart(Ether* edev)
|
|
{
|
|
Td *td;
|
|
int size;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
while(ctlr->ntd < Ntd){
|
|
bp = qget(edev->oq);
|
|
if(bp == nil)
|
|
break;
|
|
size = BLEN(bp);
|
|
|
|
td = &ctlr->td[ctlr->tdh];
|
|
if(((uintptr)bp->rp) & 0x03){
|
|
memmove(td->data, bp->rp, size);
|
|
freeb(bp);
|
|
csr32w(ctlr, td->tsad, PCIWADDR(td->data));
|
|
ctlr->tunaligned++;
|
|
}
|
|
else{
|
|
td->bp = bp;
|
|
csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
|
|
ctlr->taligned++;
|
|
}
|
|
csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
|
|
|
|
ctlr->ntd++;
|
|
ctlr->tdh = NEXT(ctlr->tdh, Ntd);
|
|
}
|
|
}
|
|
|
|
static void
|
|
rtl8139transmit(Ether* edev)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
ilock(&ctlr->tlock);
|
|
rtl8139txstart(edev);
|
|
iunlock(&ctlr->tlock);
|
|
}
|
|
|
|
static void
|
|
rtl8139receive(Ether* edev)
|
|
{
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
ushort capr;
|
|
uchar cr, *p;
|
|
int l, length, status;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
/*
|
|
* Capr is where the host is reading from,
|
|
* Cbr is where the NIC is currently writing.
|
|
*/
|
|
capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
|
|
while(!(csr8r(ctlr, Cr) & Bufe)){
|
|
p = ctlr->rbstart+capr;
|
|
|
|
/*
|
|
* Apparently the packet length may be 0xFFF0 if
|
|
* the NIC is still copying the packet into memory.
|
|
*/
|
|
length = (*(p+3)<<8)|*(p+2);
|
|
if(length == 0xFFF0)
|
|
break;
|
|
status = (*(p+1)<<8)|*p;
|
|
|
|
if(!(status & Rcok)){
|
|
if(status & (Ise|Fae))
|
|
edev->frames++;
|
|
if(status & Crc)
|
|
edev->crcs++;
|
|
if(status & (Runt|Long))
|
|
edev->buffs++;
|
|
|
|
/*
|
|
* Reset the receiver.
|
|
* Also may have to restore the multicast list
|
|
* here too if it ever gets used.
|
|
*/
|
|
cr = csr8r(ctlr, Cr);
|
|
csr8w(ctlr, Cr, cr & ~Re);
|
|
csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
|
|
csr8w(ctlr, Cr, cr);
|
|
csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Receive Completed OK.
|
|
* Very simplistic; there are ways this could be done
|
|
* without copying, but the juice probably isn't worth
|
|
* the squeeze.
|
|
* The packet length includes a 4 byte CRC on the end.
|
|
*/
|
|
capr = (capr+4) % ctlr->rblen;
|
|
p = ctlr->rbstart+capr;
|
|
capr = (capr+length) % ctlr->rblen;
|
|
if(status & Mar)
|
|
ctlr->mcast++;
|
|
|
|
if((bp = iallocb(length)) != nil){
|
|
if(p+length >= ctlr->rbstart+ctlr->rblen){
|
|
l = ctlr->rbstart+ctlr->rblen - p;
|
|
memmove(bp->wp, p, l);
|
|
bp->wp += l;
|
|
length -= l;
|
|
p = ctlr->rbstart;
|
|
}
|
|
if(length > 0){
|
|
memmove(bp->wp, p, length);
|
|
bp->wp += length;
|
|
}
|
|
bp->wp -= 4;
|
|
etheriq(edev, bp, 1);
|
|
}
|
|
|
|
capr = ROUNDUP(capr, 4);
|
|
csr16w(ctlr, Capr, capr-16);
|
|
}
|
|
}
|
|
|
|
static void
|
|
rtl8139interrupt(Ureg*, void* arg)
|
|
{
|
|
Td *td;
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
int isr, msr, tsd;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
while((isr = csr16r(ctlr, Isr)) != 0){
|
|
csr16w(ctlr, Isr, isr);
|
|
if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
|
|
rtl8139receive(edev);
|
|
if(!(isr & Rok))
|
|
ctlr->ierrs++;
|
|
isr &= ~(Fovw|Rxovw|Rer|Rok);
|
|
}
|
|
|
|
if(isr & (Ter|Tok)){
|
|
ilock(&ctlr->tlock);
|
|
while(ctlr->ntd){
|
|
td = &ctlr->td[ctlr->tdi];
|
|
tsd = csr32r(ctlr, td->tsd);
|
|
if(!(tsd & (Tabt|Tun|Tcok)))
|
|
break;
|
|
|
|
if(!(tsd & Tcok)){
|
|
if(tsd & Tun){
|
|
if(ctlr->etxth < ETHERMAXTU/32)
|
|
ctlr->etxth++;
|
|
}
|
|
edev->oerrs++;
|
|
}
|
|
|
|
if(td->bp != nil){
|
|
freeb(td->bp);
|
|
td->bp = nil;
|
|
}
|
|
|
|
ctlr->ntd--;
|
|
ctlr->tdi = NEXT(ctlr->tdi, Ntd);
|
|
}
|
|
rtl8139txstart(edev);
|
|
iunlock(&ctlr->tlock);
|
|
isr &= ~(Ter|Tok);
|
|
}
|
|
|
|
if(isr & PunLc){
|
|
/*
|
|
* Maybe the link changed - do we care very much?
|
|
*/
|
|
msr = csr8r(ctlr, Msr);
|
|
if(!(msr & Linkb)){
|
|
if(!(msr & Speed10) && edev->mbps != 100){
|
|
edev->mbps = 100;
|
|
qsetlimit(edev->oq, 256*1024);
|
|
}
|
|
else if((msr & Speed10) && edev->mbps != 10){
|
|
edev->mbps = 10;
|
|
qsetlimit(edev->oq, 65*1024);
|
|
}
|
|
}
|
|
isr &= ~(Clc|PunLc);
|
|
}
|
|
|
|
/*
|
|
* Only Serr|Timerbit should be left by now.
|
|
* Should anything be done to tidy up? TimerInt isn't
|
|
* used so that can be cleared. A PCI bus error is indicated
|
|
* by Serr, that's pretty serious; is there anyhing to do
|
|
* other than try to reinitialise the chip?
|
|
*/
|
|
if((isr & (Serr|Timerbit)) != 0){
|
|
iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
|
|
csr16r(ctlr, Imr), isr);
|
|
if(isr & Timerbit)
|
|
csr32w(ctlr, TimerInt, 0);
|
|
if(isr & Serr)
|
|
rtl8139init(edev);
|
|
}
|
|
}
|
|
}
|
|
|
|
static Ctlr*
|
|
rtl8139match(Ether* edev, int id)
|
|
{
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
int i, port;
|
|
|
|
/*
|
|
* Any adapter matches if no edev->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
p = ctlr->pcidev;
|
|
if(((p->did<<16)|p->vid) != id)
|
|
continue;
|
|
port = p->mem[0].bar & ~0x01;
|
|
if(edev->port != 0 && edev->port != port)
|
|
continue;
|
|
|
|
if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
|
|
print("rtl8139: port %#ux in use\n", port);
|
|
continue;
|
|
}
|
|
|
|
if(pcigetpms(p) > 0){
|
|
pcisetpms(p, 0);
|
|
|
|
for(i = 0; i < 6; i++)
|
|
pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
|
|
pcicfgw8(p, PciINTL, p->intl);
|
|
pcicfgw8(p, PciLTR, p->ltr);
|
|
pcicfgw8(p, PciCLS, p->cls);
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
ctlr->port = port;
|
|
if(rtl8139reset(ctlr)) {
|
|
iofree(port);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
|
|
ctlr->active = 1;
|
|
return ctlr;
|
|
}
|
|
return nil;
|
|
}
|
|
|
|
static struct {
|
|
char* name;
|
|
int id;
|
|
} rtl8139pci[] = {
|
|
{ "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */
|
|
{ "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
|
|
{ "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
|
|
{ "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
|
|
{ nil },
|
|
};
|
|
|
|
static int
|
|
rtl8139pnp(Ether* edev)
|
|
{
|
|
int i, id;
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
uchar ea[Eaddrlen];
|
|
|
|
/*
|
|
* Make a list of all ethernet controllers
|
|
* if not already done.
|
|
*/
|
|
if(ctlrhead == nil){
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != 0x02 || p->ccru != 0)
|
|
continue;
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
if(ctlr == nil){
|
|
print("rtl8139: can't allocate memory\n");
|
|
continue;
|
|
}
|
|
ctlr->pcidev = p;
|
|
ctlr->id = (p->did<<16)|p->vid;
|
|
|
|
if(ctlrhead != nil)
|
|
ctlrtail->next = ctlr;
|
|
else
|
|
ctlrhead = ctlr;
|
|
ctlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Is it an RTL8139 under a different name?
|
|
* Normally a search is made through all the found controllers
|
|
* for one which matches any of the known vid+did pairs.
|
|
* If a vid+did pair is specified a search is made for that
|
|
* specific controller only.
|
|
*/
|
|
id = 0;
|
|
for(i = 0; i < edev->nopt; i++){
|
|
if(cistrncmp(edev->opt[i], "id=", 3) == 0)
|
|
id = strtol(&edev->opt[i][3], nil, 0);
|
|
}
|
|
|
|
ctlr = nil;
|
|
if(id != 0)
|
|
ctlr = rtl8139match(edev, id);
|
|
else for(i = 0; rtl8139pci[i].name; i++){
|
|
if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
|
|
break;
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pcidev->intl;
|
|
edev->tbdf = ctlr->pcidev->tbdf;
|
|
|
|
/*
|
|
* Check if the adapter's station address is to be overridden.
|
|
* If not, read it from the device and set in edev->ea.
|
|
*/
|
|
memset(ea, 0, Eaddrlen);
|
|
if(memcmp(ea, edev->ea, Eaddrlen) == 0){
|
|
i = csr32r(ctlr, Idr0);
|
|
edev->ea[0] = i;
|
|
edev->ea[1] = i>>8;
|
|
edev->ea[2] = i>>16;
|
|
edev->ea[3] = i>>24;
|
|
i = csr32r(ctlr, Idr0+4);
|
|
edev->ea[4] = i;
|
|
edev->ea[5] = i>>8;
|
|
}
|
|
|
|
edev->attach = rtl8139attach;
|
|
edev->transmit = rtl8139transmit;
|
|
edev->interrupt = rtl8139interrupt;
|
|
edev->ifstat = rtl8139ifstat;
|
|
|
|
edev->arg = edev;
|
|
edev->promiscuous = rtl8139promiscuous;
|
|
edev->multicast = rtl8139multicast;
|
|
// edev->shutdown = rtl8139shutdown;
|
|
|
|
/*
|
|
* This should be much more dynamic but will do for now.
|
|
*/
|
|
if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
|
|
edev->mbps = 100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ether8139link(void)
|
|
{
|
|
addethercard("rtl8139", rtl8139pnp);
|
|
}
|