1248 lines
29 KiB
C
Executable file
1248 lines
29 KiB
C
Executable file
/*
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* National Semiconductor DP83820
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* 10/100/1000 Mb/s Ethernet Network Interface Controller
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* (Gig-NIC).
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* Driver assumes little-endian and 32-bit host throughout.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#include "ethermii.h"
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enum { /* Registers */
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Cr = 0x00, /* Command */
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Cfg = 0x04, /* Configuration and Media Status */
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Mear = 0x08, /* MII/EEPROM Access */
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Ptscr = 0x0C, /* PCI Test Control */
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Isr = 0x10, /* Interrupt Status */
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Imr = 0x14, /* Interrupt Mask */
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Ier = 0x18, /* Interrupt Enable */
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Ihr = 0x1C, /* Interrupt Holdoff */
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Txdp = 0x20, /* Transmit Descriptor Pointer */
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Txdphi = 0x24, /* Transmit Descriptor Pointer Hi */
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Txcfg = 0x28, /* Transmit Configuration */
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Gpior = 0x2C, /* General Purpose I/O Control */
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Rxdp = 0x30, /* Receive Descriptor Pointer */
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Rxdphi = 0x34, /* Receive Descriptor Pointer Hi */
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Rxcfg = 0x38, /* Receive Configuration */
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Pqcr = 0x3C, /* Priority Queueing Control */
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Wcsr = 0x40, /* Wake on LAN Control/Status */
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Pcr = 0x44, /* Pause Control/Status */
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Rfcr = 0x48, /* Receive Filter/Match Control */
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Rfdr = 0x4C, /* Receive Filter/Match Data */
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Brar = 0x50, /* Boot ROM Address */
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Brdr = 0x54, /* Boot ROM Data */
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Srr = 0x58, /* Silicon Revision */
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Mibc = 0x5C, /* MIB Control */
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Mibd = 0x60, /* MIB Data */
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Txdp1 = 0xA0, /* Txdp Priority 1 */
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Txdp2 = 0xA4, /* Txdp Priority 2 */
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Txdp3 = 0xA8, /* Txdp Priority 3 */
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Rxdp1 = 0xB0, /* Rxdp Priority 1 */
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Rxdp2 = 0xB4, /* Rxdp Priority 2 */
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Rxdp3 = 0xB8, /* Rxdp Priority 3 */
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Vrcr = 0xBC, /* VLAN/IP Receive Control */
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Vtcr = 0xC0, /* VLAN/IP Transmit Control */
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Vdr = 0xC4, /* VLAN Data */
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Ccsr = 0xCC, /* Clockrun Control/Status */
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Tbicr = 0xE0, /* TBI Control */
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Tbisr = 0xE4, /* TBI Status */
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Tanar = 0xE8, /* TBI ANAR */
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Tanlpar = 0xEC, /* TBI ANLPAR */
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Taner = 0xF0, /* TBI ANER */
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Tesr = 0xF4, /* TBI ESR */
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};
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enum { /* Cr */
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Txe = 0x00000001, /* Transmit Enable */
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Txd = 0x00000002, /* Transmit Disable */
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Rxe = 0x00000004, /* Receiver Enable */
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Rxd = 0x00000008, /* Receiver Disable */
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Txr = 0x00000010, /* Transmitter Reset */
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Rxr = 0x00000020, /* Receiver Reset */
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Swien = 0x00000080, /* Software Interrupt Enable */
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Rst = 0x00000100, /* Reset */
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TxpriSHFT = 9, /* Tx Priority Queue Select */
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TxpriMASK = 0x00001E00,
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RxpriSHFT = 13, /* Rx Priority Queue Select */
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RxpriMASK = 0x0001E000,
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};
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enum { /* Configuration and Media Status */
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Bem = 0x00000001, /* Big Endian Mode */
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Ext125 = 0x00000002, /* External 125MHz reference Select */
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Bromdis = 0x00000004, /* Disable Boot ROM interface */
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Pesel = 0x00000008, /* Parity Error Detection Action */
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Exd = 0x00000010, /* Excessive Deferral Abort */
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Pow = 0x00000020, /* Program Out of Window Timer */
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Sb = 0x00000040, /* Single Back-off */
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Reqalg = 0x00000080, /* PCI Bus Request Algorithm */
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Extstsen = 0x00000100, /* Extended Status Enable */
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Phydis = 0x00000200, /* Disable PHY */
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Phyrst = 0x00000400, /* Reset PHY */
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M64addren = 0x00000800, /* Master 64-bit Addressing Enable */
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Data64en = 0x00001000, /* 64-bit Data Enable */
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Pci64det = 0x00002000, /* PCI 64-bit Bus Detected */
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T64addren = 0x00004000, /* Target 64-bit Addressing Enable */
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Mwidis = 0x00008000, /* MWI Disable */
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Mrmdis = 0x00010000, /* MRM Disable */
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Tmrtest = 0x00020000, /* Timer Test Mode */
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Spdstsien = 0x00040000, /* PHY Spdsts Interrupt Enable */
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Lnkstsien = 0x00080000, /* PHY Lnksts Interrupt Enable */
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Dupstsien = 0x00100000, /* PHY Dupsts Interrupt Enable */
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Mode1000 = 0x00400000, /* 1000Mb/s Mode Control */
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Tbien = 0x01000000, /* Ten-Bit Interface Enable */
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Dupsts = 0x10000000, /* Full Duplex Status */
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Spdsts100 = 0x20000000, /* SPEED100 Input Pin Status */
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Spdsts1000 = 0x40000000, /* SPEED1000 Input Pin Status */
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Lnksts = 0x80000000, /* Link Status */
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};
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enum { /* MII/EEPROM Access */
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Eedi = 0x00000001, /* EEPROM Data In */
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Eedo = 0x00000002, /* EEPROM Data Out */
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Eeclk = 0x00000004, /* EEPROM Serial Clock */
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Eesel = 0x00000008, /* EEPROM Chip Select */
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Mdio = 0x00000010, /* MII Management Data */
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Mddir = 0x00000020, /* MII Management Direction */
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Mdc = 0x00000040, /* MII Management Clock */
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};
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enum { /* Interrupts */
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Rxok = 0x00000001, /* Rx OK */
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Rxdesc = 0x00000002, /* Rx Descriptor */
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Rxerr = 0x00000004, /* Rx Packet Error */
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Rxearly = 0x00000008, /* Rx Early Threshold */
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Rxidle = 0x00000010, /* Rx Idle */
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Rxorn = 0x00000020, /* Rx Overrun */
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Txok = 0x00000040, /* Tx Packet OK */
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Txdesc = 0x00000080, /* Tx Descriptor */
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Txerr = 0x00000100, /* Tx Packet Error */
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Txidle = 0x00000200, /* Tx Idle */
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Txurn = 0x00000400, /* Tx Underrun */
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Mib = 0x00000800, /* MIB Service */
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Swi = 0x00001000, /* Software Interrupt */
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Pme = 0x00002000, /* Power Management Event */
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Phy = 0x00004000, /* PHY Interrupt */
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Hibint = 0x00008000, /* High Bits Interrupt Set */
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Rxsovr = 0x00010000, /* Rx Status FIFO Overrun */
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Rtabt = 0x00020000, /* Received Target Abort */
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Rmabt = 0x00040000, /* Received Master Abort */
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Sserr = 0x00080000, /* Signalled System Error */
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Dperr = 0x00100000, /* Detected Parity Error */
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Rxrcmp = 0x00200000, /* Receive Reset Complete */
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Txrcmp = 0x00400000, /* Transmit Reset Complete */
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Rxdesc0 = 0x00800000, /* Rx Descriptor for Priority Queue 0 */
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Rxdesc1 = 0x01000000, /* Rx Descriptor for Priority Queue 1 */
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Rxdesc2 = 0x02000000, /* Rx Descriptor for Priority Queue 2 */
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Rxdesc3 = 0x04000000, /* Rx Descriptor for Priority Queue 3 */
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Txdesc0 = 0x08000000, /* Tx Descriptor for Priority Queue 0 */
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Txdesc1 = 0x10000000, /* Tx Descriptor for Priority Queue 1 */
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Txdesc2 = 0x20000000, /* Tx Descriptor for Priority Queue 2 */
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Txdesc3 = 0x40000000, /* Tx Descriptor for Priority Queue 3 */
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};
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enum { /* Interrupt Enable */
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Ien = 0x00000001, /* Interrupt Enable */
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};
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enum { /* Interrupt Holdoff */
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IhSHFT = 0, /* Interrupt Holdoff */
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IhMASK = 0x000000FF,
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Ihctl = 0x00000100, /* Interrupt Holdoff Control */
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};
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enum { /* Transmit Configuration */
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TxdrthSHFT = 0, /* Tx Drain Threshold */
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TxdrthMASK = 0x000000FF,
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FlthSHFT = 16, /* Tx Fill Threshold */
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FlthMASK = 0x0000FF00,
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Brstdis = 0x00080000, /* 1000Mb/s Burst Disable */
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MxdmaSHFT = 20, /* Max Size per Tx DMA Burst */
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MxdmaMASK = 0x00700000,
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Ecretryen = 0x00800000, /* Excessive Collision Retry Enable */
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Atp = 0x10000000, /* Automatic Transmit Padding */
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Mlb = 0x20000000, /* MAC Loopback */
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Hbi = 0x40000000, /* Heartbeat Ignore */
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Csi = 0x80000000, /* Carrier Sense Ignore */
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};
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enum { /* Receive Configuration */
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RxdrthSHFT = 1, /* Rx Drain Threshold */
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RxdrthMASK = 0x0000003E,
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Airl = 0x04000000, /* Accept In-Range Length Errored */
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Alp = 0x08000000, /* Accept Long Packets */
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Rxfd = 0x10000000, /* Receive Full Duplex */
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Stripcrc = 0x20000000, /* Strip CRC */
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Arp = 0x40000000, /* Accept Runt Packets */
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Aep = 0x80000000, /* Accept Errored Packets */
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};
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enum { /* Priority Queueing Control */
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Txpqen = 0x00000001, /* Transmit Priority Queuing Enable */
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Txfairen = 0x00000002, /* Transmit Fairness Enable */
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RxpqenSHFT = 2, /* Receive Priority Queue Enable */
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RxpqenMASK = 0x0000000C,
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};
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enum { /* Pause Control/Status */
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PscntSHFT = 0, /* Pause Counter Value */
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PscntMASK = 0x0000FFFF,
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Pstx = 0x00020000, /* Transmit Pause Frame */
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PsffloSHFT = 18, /* Rx Data FIFO Lo Threshold */
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PsffloMASK = 0x000C0000,
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PsffhiSHFT = 20, /* Rx Data FIFO Hi Threshold */
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PsffhiMASK = 0x00300000,
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PsstloSHFT = 22, /* Rx Stat FIFO Hi Threshold */
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PsstloMASK = 0x00C00000,
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PssthiSHFT = 24, /* Rx Stat FIFO Hi Threshold */
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PssthiMASK = 0x03000000,
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Psrcvd = 0x08000000, /* Pause Frame Received */
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Psact = 0x10000000, /* Pause Active */
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Psda = 0x20000000, /* Pause on Destination Address */
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Psmcast = 0x40000000, /* Pause on Multicast */
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Psen = 0x80000000, /* Pause Enable */
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};
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enum { /* Receive Filter/Match Control */
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RfaddrSHFT = 0, /* Extended Register Address */
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RfaddrMASK = 0x000003FF,
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Ulm = 0x00080000, /* U/L bit mask */
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Uhen = 0x00100000, /* Unicast Hash Enable */
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Mhen = 0x00200000, /* Multicast Hash Enable */
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Aarp = 0x00400000, /* Accept ARP Packets */
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ApatSHFT = 23, /* Accept on Pattern Match */
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ApatMASK = 0x07800000,
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Apm = 0x08000000, /* Accept on Perfect Match */
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Aau = 0x10000000, /* Accept All Unicast */
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Aam = 0x20000000, /* Accept All Multicast */
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Aab = 0x40000000, /* Accept All Broadcast */
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Rfen = 0x80000000, /* Rx Filter Enable */
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};
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enum { /* Receive Filter/Match Data */
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RfdataSHFT = 0, /* Receive Filter Data */
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RfdataMASK = 0x0000FFFF,
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BmaskSHFT = 16, /* Byte Mask */
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BmaskMASK = 0x00030000,
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};
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enum { /* MIB Control */
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Wrn = 0x00000001, /* Warning Test Indicator */
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Frz = 0x00000002, /* Freeze All Counters */
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Aclr = 0x00000004, /* Clear All Counters */
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Mibs = 0x00000008, /* MIB Counter Strobe */
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};
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enum { /* MIB Data */
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Nmibd = 11, /* Number of MIB Data Registers */
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};
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enum { /* VLAN/IP Receive Control */
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Vtden = 0x00000001, /* VLAN Tag Detection Enable */
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Vtren = 0x00000002, /* VLAN Tag Removal Enable */
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Dvtf = 0x00000004, /* Discard VLAN Tagged Frames */
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Dutf = 0x00000008, /* Discard Untagged Frames */
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Ipen = 0x00000010, /* IP Checksum Enable */
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Ripe = 0x00000020, /* Reject IP Checksum Errors */
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Rtcpe = 0x00000040, /* Reject TCP Checksum Errors */
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Rudpe = 0x00000080, /* Reject UDP Checksum Errors */
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};
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enum { /* VLAN/IP Transmit Control */
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Vgti = 0x00000001, /* VLAN Global Tag Insertion */
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Vppti = 0x00000002, /* VLAN Per-Packet Tag Insertion */
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Gchk = 0x00000004, /* Global Checksum Generation */
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Ppchk = 0x00000008, /* Per-Packet Checksum Generation */
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};
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enum { /* VLAN Data */
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VtypeSHFT = 0, /* VLAN Type Field */
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VtypeMASK = 0x0000FFFF,
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VtciSHFT = 16, /* VLAN Tag Control Information */
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VtciMASK = 0xFFFF0000,
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};
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enum { /* Clockrun Control/Status */
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Clkrunen = 0x00000001, /* CLKRUN Enable */
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Pmeen = 0x00000100, /* PME Enable */
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Pmests = 0x00008000, /* PME Status */
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};
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typedef struct {
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u32int link; /* Link to the next descriptor */
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u32int bufptr; /* pointer to data Buffer */
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int cmdsts; /* Command/Status */
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int extsts; /* optional Extended Status */
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Block* bp; /* Block containing bufptr */
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u32int unused; /* pad to 64-bit */
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} Desc;
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enum { /* Common cmdsts bits */
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SizeMASK = 0x0000FFFF, /* Descriptor Byte Count */
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SizeSHFT = 0,
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Ok = 0x08000000, /* Packet OK */
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Crc = 0x10000000, /* Suppress/Include CRC */
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Intr = 0x20000000, /* Interrupt on ownership transfer */
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More = 0x40000000, /* not last descriptor in a packet */
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Own = 0x80000000, /* Descriptor Ownership */
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};
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enum { /* Transmit cmdsts bits */
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CcntMASK = 0x000F0000, /* Collision Count */
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CcntSHFT = 16,
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Ec = 0x00100000, /* Excessive Collisions */
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Owc = 0x00200000, /* Out of Window Collision */
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Ed = 0x00400000, /* Excessive Deferral */
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Td = 0x00800000, /* Transmit Deferred */
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Crs = 0x01000000, /* Carrier Sense Lost */
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Tfu = 0x02000000, /* Transmit FIFO Underrun */
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Txa = 0x04000000, /* Transmit Abort */
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};
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enum { /* Receive cmdsts bits */
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Irl = 0x00010000, /* In-Range Length Error */
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Lbp = 0x00020000, /* Loopback Packet */
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Fae = 0x00040000, /* Frame Alignment Error */
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Crce = 0x00080000, /* CRC Error */
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Ise = 0x00100000, /* Invalid Symbol Error */
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Runt = 0x00200000, /* Runt Packet Received */
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Long = 0x00400000, /* Too Long Packet Received */
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DestMASK = 0x01800000, /* Destination Class */
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DestSHFT = 23,
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Rxo = 0x02000000, /* Receive Overrun */
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Rxa = 0x04000000, /* Receive Aborted */
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};
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enum { /* extsts bits */
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EvtciMASK = 0x0000FFFF, /* VLAN Tag Control Information */
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EvtciSHFT = 0,
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Vpkt = 0x00010000, /* VLAN Packet */
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Ippkt = 0x00020000, /* IP Packet */
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Iperr = 0x00040000, /* IP Checksum Error */
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Tcppkt = 0x00080000, /* TCP Packet */
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Tcperr = 0x00100000, /* TCP Checksum Error */
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Udppkt = 0x00200000, /* UDP Packet */
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Udperr = 0x00400000, /* UDP Checksum Error */
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};
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enum {
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Nrd = 256,
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Nrb = 4*Nrd,
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Rbsz = ROUNDUP(sizeof(Etherpkt)+8, 8),
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Ntd = 128,
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};
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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int id;
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int eepromsz; /* address size in bits */
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ushort* eeprom;
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int* nic;
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int cfg;
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int imr;
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QLock alock; /* attach */
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Lock ilock; /* init */
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void* alloc; /* base of per-Ctlr allocated data */
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Mii* mii;
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Lock rdlock; /* receive */
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Desc* rd;
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int nrd;
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int nrb;
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int rdx;
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int rxcfg;
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Lock tlock; /* transmit */
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Desc* td;
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int ntd;
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int tdh;
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int tdt;
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int ntq;
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int txcfg;
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int rxidle;
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uint mibd[Nmibd];
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int ec;
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int owc;
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int ed;
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int crs;
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int tfu;
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int txa;
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} Ctlr;
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#define csr32r(c, r) (*((c)->nic+((r)/4)))
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#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
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static Ctlr* dp83820ctlrhead;
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static Ctlr* dp83820ctlrtail;
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static Lock dp83820rblock; /* free receive Blocks */
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static Block* dp83820rbpool;
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static char* dp83820mibs[Nmibd] = {
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"RXErroredPkts",
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"RXFCSErrors",
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"RXMsdPktErrors",
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"RXFAErrors",
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"RXSymbolErrors",
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"RXFrameToLong",
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"RXIRLErrors",
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"RXBadOpcodes",
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"RXPauseFrames",
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"TXPauseFrames",
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"TXSQEErrors",
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};
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static int
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mdior(Ctlr* ctlr, int n)
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{
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int data, i, mear, r;
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mear = csr32r(ctlr, Mear);
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r = ~(Mdc|Mddir) & mear;
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data = 0;
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for(i = n-1; i >= 0; i--){
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if(csr32r(ctlr, Mear) & Mdio)
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data |= (1<<i);
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csr32w(ctlr, Mear, Mdc|r);
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csr32w(ctlr, Mear, r);
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}
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csr32w(ctlr, Mear, mear);
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return data;
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}
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static void
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mdiow(Ctlr* ctlr, int bits, int n)
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{
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int i, mear, r;
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mear = csr32r(ctlr, Mear);
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r = Mddir|(~Mdc & mear);
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for(i = n-1; i >= 0; i--){
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if(bits & (1<<i))
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r |= Mdio;
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else
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r &= ~Mdio;
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csr32w(ctlr, Mear, r);
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csr32w(ctlr, Mear, Mdc|r);
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}
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csr32w(ctlr, Mear, mear);
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}
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static int
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dp83820miimir(Mii* mii, int pa, int ra)
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{
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int data;
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Ctlr *ctlr;
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ctlr = mii->ctlr;
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/*
|
|
* MII Management Interface Read.
|
|
*
|
|
* Preamble;
|
|
* ST+OP+PA+RA;
|
|
* LT + 16 data bits.
|
|
*/
|
|
mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
|
|
data = mdior(ctlr, 18);
|
|
|
|
if(data & 0x10000)
|
|
return -1;
|
|
|
|
return data & 0xFFFF;
|
|
}
|
|
|
|
static int
|
|
dp83820miimiw(Mii* mii, int pa, int ra, int data)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
/*
|
|
* MII Management Interface Write.
|
|
*
|
|
* Preamble;
|
|
* ST+OP+PA+RA+LT + 16 data bits;
|
|
* Z.
|
|
*/
|
|
mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
data &= 0xFFFF;
|
|
data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
|
|
mdiow(ctlr, data, 32);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static Block *
|
|
dp83820rballoc(Desc* desc)
|
|
{
|
|
Block *bp;
|
|
|
|
if(desc->bp == nil){
|
|
ilock(&dp83820rblock);
|
|
if((bp = dp83820rbpool) == nil){
|
|
iunlock(&dp83820rblock);
|
|
desc->bp = nil;
|
|
desc->cmdsts = Own;
|
|
return nil;
|
|
}
|
|
dp83820rbpool = bp->next;
|
|
bp->next = nil;
|
|
_xinc(&bp->ref); /* prevent bp from being freed */
|
|
iunlock(&dp83820rblock);
|
|
|
|
desc->bufptr = PCIWADDR(bp->rp);
|
|
desc->bp = bp;
|
|
}
|
|
else{
|
|
bp = desc->bp;
|
|
bp->rp = bp->lim - Rbsz;
|
|
bp->wp = bp->rp;
|
|
}
|
|
|
|
coherence();
|
|
desc->cmdsts = Intr|Rbsz;
|
|
|
|
return bp;
|
|
}
|
|
|
|
static void
|
|
dp83820rbfree(Block *bp)
|
|
{
|
|
bp->rp = bp->lim - Rbsz;
|
|
bp->wp = bp->rp;
|
|
|
|
ilock(&dp83820rblock);
|
|
bp->next = dp83820rbpool;
|
|
dp83820rbpool = bp;
|
|
iunlock(&dp83820rblock);
|
|
}
|
|
|
|
static void
|
|
dp83820halt(Ctlr* ctlr)
|
|
{
|
|
int i, timeo;
|
|
|
|
ilock(&ctlr->ilock);
|
|
csr32w(ctlr, Imr, 0);
|
|
csr32w(ctlr, Ier, 0);
|
|
csr32w(ctlr, Cr, Rxd|Txd);
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr32r(ctlr, Cr) & (Rxe|Txe)))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
csr32w(ctlr, Mibc, Frz);
|
|
iunlock(&ctlr->ilock);
|
|
|
|
if(ctlr->rd != nil){
|
|
for(i = 0; i < ctlr->nrd; i++){
|
|
if(ctlr->rd[i].bp == nil)
|
|
continue;
|
|
freeb(ctlr->rd[i].bp);
|
|
ctlr->rd[i].bp = nil;
|
|
}
|
|
}
|
|
if(ctlr->td != nil){
|
|
for(i = 0; i < ctlr->ntd; i++){
|
|
if(ctlr->td[i].bp == nil)
|
|
continue;
|
|
freeb(ctlr->td[i].bp);
|
|
ctlr->td[i].bp = nil;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
dp83820cfg(Ctlr* ctlr)
|
|
{
|
|
int cfg;
|
|
|
|
/*
|
|
* Don't know how to deal with a TBI yet.
|
|
*/
|
|
if(ctlr->mii == nil)
|
|
return;
|
|
|
|
/*
|
|
* The polarity of these bits is at the mercy
|
|
* of the board designer.
|
|
* The correct answer for all speed and duplex questions
|
|
* should be to query the phy.
|
|
*/
|
|
cfg = csr32r(ctlr, Cfg);
|
|
if(!(cfg & Dupsts)){
|
|
ctlr->rxcfg |= Rxfd;
|
|
ctlr->txcfg |= Csi|Hbi;
|
|
iprint("83820: full duplex, ");
|
|
}
|
|
else{
|
|
ctlr->rxcfg &= ~Rxfd;
|
|
ctlr->txcfg &= ~(Csi|Hbi);
|
|
iprint("83820: half duplex, ");
|
|
}
|
|
csr32w(ctlr, Rxcfg, ctlr->rxcfg);
|
|
csr32w(ctlr, Txcfg, ctlr->txcfg);
|
|
|
|
switch(cfg & (Spdsts1000|Spdsts100)){
|
|
case Spdsts1000: /* 100Mbps */
|
|
default: /* 10Mbps */
|
|
ctlr->cfg &= ~Mode1000;
|
|
if((cfg & (Spdsts1000|Spdsts100)) == Spdsts1000)
|
|
iprint("100Mb/s\n");
|
|
else
|
|
iprint("10Mb/s\n");
|
|
break;
|
|
case Spdsts100: /* 1Gbps */
|
|
ctlr->cfg |= Mode1000;
|
|
iprint("1Gb/s\n");
|
|
break;
|
|
}
|
|
csr32w(ctlr, Cfg, ctlr->cfg);
|
|
}
|
|
|
|
static void
|
|
dp83820init(Ether* edev)
|
|
{
|
|
int i;
|
|
Ctlr *ctlr;
|
|
Desc *desc;
|
|
uchar *alloc;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
dp83820halt(ctlr);
|
|
|
|
/*
|
|
* Receiver
|
|
*/
|
|
alloc = (uchar*)ROUNDUP((ulong)ctlr->alloc, 8);
|
|
ctlr->rd = (Desc*)alloc;
|
|
alloc += ctlr->nrd*sizeof(Desc);
|
|
memset(ctlr->rd, 0, ctlr->nrd*sizeof(Desc));
|
|
ctlr->rdx = 0;
|
|
for(i = 0; i < ctlr->nrd; i++){
|
|
desc = &ctlr->rd[i];
|
|
desc->link = PCIWADDR(&ctlr->rd[NEXT(i, ctlr->nrd)]);
|
|
if(dp83820rballoc(desc) == nil)
|
|
continue;
|
|
}
|
|
csr32w(ctlr, Rxdphi, 0);
|
|
csr32w(ctlr, Rxdp, PCIWADDR(ctlr->rd));
|
|
|
|
for(i = 0; i < Eaddrlen; i += 2){
|
|
csr32w(ctlr, Rfcr, i);
|
|
csr32w(ctlr, Rfdr, (edev->ea[i+1]<<8)|edev->ea[i]);
|
|
}
|
|
csr32w(ctlr, Rfcr, Rfen|Aab|Aam|Apm);
|
|
|
|
ctlr->rxcfg = Stripcrc|(((2*(ETHERMINTU+4))/8)<<RxdrthSHFT);
|
|
ctlr->imr |= Rxorn|Rxidle|Rxearly|Rxdesc|Rxok;
|
|
|
|
/*
|
|
* Transmitter.
|
|
*/
|
|
ctlr->td = (Desc*)alloc;
|
|
memset(ctlr->td, 0, ctlr->ntd*sizeof(Desc));
|
|
ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
|
|
for(i = 0; i < ctlr->ntd; i++){
|
|
desc = &ctlr->td[i];
|
|
desc->link = PCIWADDR(&ctlr->td[NEXT(i, ctlr->ntd)]);
|
|
}
|
|
csr32w(ctlr, Txdphi, 0);
|
|
csr32w(ctlr, Txdp, PCIWADDR(ctlr->td));
|
|
|
|
ctlr->txcfg = Atp|(((2*(ETHERMINTU+4))/32)<<FlthSHFT)|((4096/32)<<TxdrthSHFT);
|
|
ctlr->imr |= Txurn|Txidle|Txdesc|Txok;
|
|
|
|
ilock(&ctlr->ilock);
|
|
|
|
dp83820cfg(ctlr);
|
|
|
|
csr32w(ctlr, Mibc, Aclr);
|
|
ctlr->imr |= Mib;
|
|
|
|
csr32w(ctlr, Imr, ctlr->imr);
|
|
|
|
/* try coalescing adjacent interrupts; use hold-off interval of 100µs */
|
|
csr32w(ctlr, Ihr, Ihctl|(1<<IhSHFT));
|
|
|
|
csr32w(ctlr, Ier, Ien);
|
|
csr32w(ctlr, Cr, Rxe|Txe);
|
|
|
|
iunlock(&ctlr->ilock);
|
|
}
|
|
|
|
static void
|
|
dp83820attach(Ether* edev)
|
|
{
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
qlock(&ctlr->alock);
|
|
if(ctlr->alloc != nil){
|
|
qunlock(&ctlr->alock);
|
|
return;
|
|
}
|
|
|
|
if(waserror()){
|
|
if(ctlr->mii != nil){
|
|
free(ctlr->mii);
|
|
ctlr->mii = nil;
|
|
}
|
|
if(ctlr->alloc != nil){
|
|
free(ctlr->alloc);
|
|
ctlr->alloc = nil;
|
|
}
|
|
qunlock(&ctlr->alock);
|
|
nexterror();
|
|
}
|
|
|
|
if(!(ctlr->cfg & Tbien)){
|
|
if((ctlr->mii = malloc(sizeof(Mii))) == nil)
|
|
error(Enomem);
|
|
ctlr->mii->ctlr = ctlr;
|
|
ctlr->mii->mir = dp83820miimir;
|
|
ctlr->mii->miw = dp83820miimiw;
|
|
if(mii(ctlr->mii, ~0) == 0)
|
|
error("no PHY");
|
|
ctlr->cfg |= Dupstsien|Lnkstsien|Spdstsien;
|
|
ctlr->imr |= Phy;
|
|
}
|
|
|
|
ctlr->nrd = Nrd;
|
|
ctlr->nrb = Nrb;
|
|
ctlr->ntd = Ntd;
|
|
ctlr->alloc = mallocz((ctlr->nrd+ctlr->ntd)*sizeof(Desc) + 7, 0);
|
|
if(ctlr->alloc == nil)
|
|
error(Enomem);
|
|
|
|
for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){
|
|
if((bp = allocb(Rbsz)) == nil)
|
|
break;
|
|
bp->free = dp83820rbfree;
|
|
dp83820rbfree(bp);
|
|
}
|
|
|
|
dp83820init(edev);
|
|
|
|
qunlock(&ctlr->alock);
|
|
poperror();
|
|
}
|
|
|
|
static void
|
|
dp83820transmit(Ether* edev)
|
|
{
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
Desc *desc;
|
|
int cmdsts, r, x;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
ilock(&ctlr->tlock);
|
|
|
|
bp = nil;
|
|
for(x = ctlr->tdh; ctlr->ntq; x = NEXT(x, ctlr->ntd)){
|
|
desc = &ctlr->td[x];
|
|
if((cmdsts = desc->cmdsts) & Own)
|
|
break;
|
|
if(!(cmdsts & Ok)){
|
|
if(cmdsts & Ec)
|
|
ctlr->ec++;
|
|
if(cmdsts & Owc)
|
|
ctlr->owc++;
|
|
if(cmdsts & Ed)
|
|
ctlr->ed++;
|
|
if(cmdsts & Crs)
|
|
ctlr->crs++;
|
|
if(cmdsts & Tfu)
|
|
ctlr->tfu++;
|
|
if(cmdsts & Txa)
|
|
ctlr->txa++;
|
|
edev->oerrs++;
|
|
}
|
|
desc->bp->next = bp;
|
|
bp = desc->bp;
|
|
desc->bp = nil;
|
|
|
|
ctlr->ntq--;
|
|
}
|
|
ctlr->tdh = x;
|
|
if(bp != nil)
|
|
freeblist(bp);
|
|
|
|
x = ctlr->tdt;
|
|
while(ctlr->ntq < (ctlr->ntd-1)){
|
|
if((bp = qget(edev->oq)) == nil)
|
|
break;
|
|
|
|
desc = &ctlr->td[x];
|
|
desc->bufptr = PCIWADDR(bp->rp);
|
|
desc->bp = bp;
|
|
ctlr->ntq++;
|
|
coherence();
|
|
desc->cmdsts = Own|Intr|BLEN(bp);
|
|
|
|
x = NEXT(x, ctlr->ntd);
|
|
}
|
|
if(x != ctlr->tdt){
|
|
ctlr->tdt = x;
|
|
r = csr32r(ctlr, Cr);
|
|
csr32w(ctlr, Cr, Txe|r);
|
|
}
|
|
|
|
iunlock(&ctlr->tlock);
|
|
}
|
|
|
|
static void
|
|
dp83820interrupt(Ureg*, void* arg)
|
|
{
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
Desc *desc;
|
|
Ether *edev;
|
|
int cmdsts, i, isr, r, x;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
for(isr = csr32r(ctlr, Isr); isr & ctlr->imr; isr = csr32r(ctlr, Isr)){
|
|
if(isr & (Rxorn|Rxidle|Rxearly|Rxerr|Rxdesc|Rxok)){
|
|
x = ctlr->rdx;
|
|
desc = &ctlr->rd[x];
|
|
while((cmdsts = desc->cmdsts) & Own){
|
|
if((cmdsts & Ok) && desc->bp != nil){
|
|
bp = desc->bp;
|
|
desc->bp = nil;
|
|
bp->wp += cmdsts & SizeMASK;
|
|
etheriq(edev, bp, 1);
|
|
}
|
|
else if(0 && !(cmdsts & Ok)){
|
|
iprint("dp83820: rx %8.8uX:", cmdsts);
|
|
bp = desc->bp;
|
|
for(i = 0; i < 20; i++)
|
|
iprint(" %2.2uX", bp->rp[i]);
|
|
iprint("\n");
|
|
}
|
|
dp83820rballoc(desc);
|
|
|
|
x = NEXT(x, ctlr->nrd);
|
|
desc = &ctlr->rd[x];
|
|
}
|
|
ctlr->rdx = x;
|
|
|
|
if(isr & Rxidle){
|
|
r = csr32r(ctlr, Cr);
|
|
csr32w(ctlr, Cr, Rxe|r);
|
|
ctlr->rxidle++;
|
|
}
|
|
|
|
isr &= ~(Rxorn|Rxidle|Rxearly|Rxerr|Rxdesc|Rxok);
|
|
}
|
|
|
|
if(isr & Txurn){
|
|
x = (ctlr->txcfg & TxdrthMASK)>>TxdrthSHFT;
|
|
r = (ctlr->txcfg & FlthMASK)>>FlthSHFT;
|
|
if(x < ((TxdrthMASK)>>TxdrthSHFT)
|
|
&& x < (2048/32 - r)){
|
|
ctlr->txcfg &= ~TxdrthMASK;
|
|
x++;
|
|
ctlr->txcfg |= x<<TxdrthSHFT;
|
|
csr32w(ctlr, Txcfg, ctlr->txcfg);
|
|
}
|
|
}
|
|
|
|
if(isr & (Txurn|Txidle|Txdesc|Txok)){
|
|
dp83820transmit(edev);
|
|
isr &= ~(Txurn|Txidle|Txdesc|Txok);
|
|
}
|
|
|
|
if(isr & Mib){
|
|
for(i = 0; i < Nmibd; i++){
|
|
r = csr32r(ctlr, Mibd+(i*sizeof(int)));
|
|
ctlr->mibd[i] += r & 0xFFFF;
|
|
}
|
|
isr &= ~Mib;
|
|
}
|
|
|
|
if((isr & Phy) && ctlr->mii != nil){
|
|
ctlr->mii->mir(ctlr->mii, 1, Bmsr);
|
|
print("phy: cfg %8.8uX bmsr %4.4uX\n",
|
|
csr32r(ctlr, Cfg),
|
|
ctlr->mii->mir(ctlr->mii, 1, Bmsr));
|
|
dp83820cfg(ctlr);
|
|
isr &= ~Phy;
|
|
}
|
|
if(isr)
|
|
iprint("dp83820: isr %8.8uX\n", isr);
|
|
}
|
|
}
|
|
|
|
static long
|
|
dp83820ifstat(Ether* edev, void* a, long n, ulong offset)
|
|
{
|
|
char *p;
|
|
Ctlr *ctlr;
|
|
int i, l, r;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
edev->crcs = ctlr->mibd[Mibd+(1*sizeof(int))];
|
|
edev->frames = ctlr->mibd[Mibd+(3*sizeof(int))];
|
|
edev->buffs = ctlr->mibd[Mibd+(5*sizeof(int))];
|
|
edev->overflows = ctlr->mibd[Mibd+(2*sizeof(int))];
|
|
|
|
if(n == 0)
|
|
return 0;
|
|
|
|
p = malloc(READSTR);
|
|
l = 0;
|
|
for(i = 0; i < Nmibd; i++){
|
|
r = csr32r(ctlr, Mibd+(i*sizeof(int)));
|
|
ctlr->mibd[i] += r & 0xFFFF;
|
|
if(ctlr->mibd[i] != 0 && dp83820mibs[i] != nil)
|
|
l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
|
|
dp83820mibs[i], ctlr->mibd[i], r);
|
|
}
|
|
l += snprint(p+l, READSTR-l, "rxidle %d\n", ctlr->rxidle);
|
|
l += snprint(p+l, READSTR-l, "ec %d\n", ctlr->ec);
|
|
l += snprint(p+l, READSTR-l, "owc %d\n", ctlr->owc);
|
|
l += snprint(p+l, READSTR-l, "ed %d\n", ctlr->ed);
|
|
l += snprint(p+l, READSTR-l, "crs %d\n", ctlr->crs);
|
|
l += snprint(p+l, READSTR-l, "tfu %d\n", ctlr->tfu);
|
|
l += snprint(p+l, READSTR-l, "txa %d\n", ctlr->txa);
|
|
|
|
l += snprint(p+l, READSTR, "rom:");
|
|
for(i = 0; i < 0x10; i++){
|
|
if(i && ((i & 0x07) == 0))
|
|
l += snprint(p+l, READSTR-l, "\n ");
|
|
l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
|
|
}
|
|
l += snprint(p+l, READSTR-l, "\n");
|
|
|
|
if(ctlr->mii != nil && ctlr->mii->curphy != nil){
|
|
l += snprint(p+l, READSTR, "phy:");
|
|
for(i = 0; i < NMiiPhyr; i++){
|
|
if(i && ((i & 0x07) == 0))
|
|
l += snprint(p+l, READSTR-l, "\n ");
|
|
r = miimir(ctlr->mii, i);
|
|
l += snprint(p+l, READSTR-l, " %4.4uX", r);
|
|
}
|
|
snprint(p+l, READSTR-l, "\n");
|
|
}
|
|
|
|
n = readstr(offset, a, n, p);
|
|
free(p);
|
|
|
|
return n;
|
|
}
|
|
|
|
static void
|
|
dp83820promiscuous(void* arg, int on)
|
|
{
|
|
USED(arg, on);
|
|
}
|
|
|
|
/* multicast already on, don't need to do anything */
|
|
static void
|
|
dp83820multicast(void*, uchar*, int)
|
|
{
|
|
}
|
|
|
|
static int
|
|
dp83820detach(Ctlr* ctlr)
|
|
{
|
|
/*
|
|
* Soft reset the controller.
|
|
*/
|
|
csr32w(ctlr, Cr, Rst);
|
|
delay(1);
|
|
while(csr32r(ctlr, Cr) & Rst)
|
|
delay(1);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
dp83820shutdown(Ether* ether)
|
|
{
|
|
print("dp83820shutdown\n");
|
|
dp83820detach(ether->ctlr);
|
|
}
|
|
|
|
static int
|
|
atc93c46r(Ctlr* ctlr, int address)
|
|
{
|
|
int data, i, mear, r, size;
|
|
|
|
/*
|
|
* Analog Technology, Inc. ATC93C46
|
|
* or equivalent serial EEPROM.
|
|
*/
|
|
mear = csr32r(ctlr, Mear);
|
|
mear &= ~(Eesel|Eeclk|Eedo|Eedi);
|
|
r = Eesel|mear;
|
|
|
|
reread:
|
|
csr32w(ctlr, Mear, r);
|
|
data = 0x06;
|
|
for(i = 3-1; i >= 0; i--){
|
|
if(data & (1<<i))
|
|
r |= Eedi;
|
|
else
|
|
r &= ~Eedi;
|
|
csr32w(ctlr, Mear, r);
|
|
csr32w(ctlr, Mear, Eeclk|r);
|
|
microdelay(1);
|
|
csr32w(ctlr, Mear, r);
|
|
microdelay(1);
|
|
}
|
|
|
|
/*
|
|
* First time through must work out the EEPROM size.
|
|
*/
|
|
if((size = ctlr->eepromsz) == 0)
|
|
size = 8;
|
|
|
|
for(size = size-1; size >= 0; size--){
|
|
if(address & (1<<size))
|
|
r |= Eedi;
|
|
else
|
|
r &= ~Eedi;
|
|
csr32w(ctlr, Mear, r);
|
|
microdelay(1);
|
|
csr32w(ctlr, Mear, Eeclk|r);
|
|
microdelay(1);
|
|
csr32w(ctlr, Mear, r);
|
|
microdelay(1);
|
|
if(!(csr32r(ctlr, Mear) & Eedo))
|
|
break;
|
|
}
|
|
r &= ~Eedi;
|
|
|
|
data = 0;
|
|
for(i = 16-1; i >= 0; i--){
|
|
csr32w(ctlr, Mear, Eeclk|r);
|
|
microdelay(1);
|
|
if(csr32r(ctlr, Mear) & Eedo)
|
|
data |= (1<<i);
|
|
csr32w(ctlr, Mear, r);
|
|
microdelay(1);
|
|
}
|
|
|
|
csr32w(ctlr, Mear, mear);
|
|
|
|
if(ctlr->eepromsz == 0){
|
|
ctlr->eepromsz = 8-size;
|
|
ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
|
|
goto reread;
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
static int
|
|
dp83820reset(Ctlr* ctlr)
|
|
{
|
|
int i, r;
|
|
unsigned char sum;
|
|
|
|
/*
|
|
* Soft reset the controller;
|
|
* read the EEPROM to get the initial settings
|
|
* of the Cfg and Gpior bits which should be cleared by
|
|
* the reset.
|
|
*/
|
|
dp83820detach(ctlr);
|
|
|
|
atc93c46r(ctlr, 0);
|
|
if(ctlr->eeprom == nil) {
|
|
print("dp83820reset: no eeprom\n");
|
|
return -1;
|
|
}
|
|
sum = 0;
|
|
for(i = 0; i < 0x0E; i++){
|
|
r = atc93c46r(ctlr, i);
|
|
ctlr->eeprom[i] = r;
|
|
sum += r;
|
|
sum += r>>8;
|
|
}
|
|
|
|
if(sum != 0){
|
|
print("dp83820reset: bad EEPROM checksum\n");
|
|
return -1;
|
|
}
|
|
|
|
#ifdef notdef
|
|
csr32w(ctlr, Gpior, ctlr->eeprom[4]);
|
|
|
|
cfg = Extstsen|Exd;
|
|
r = csr32r(ctlr, Cfg);
|
|
if(ctlr->eeprom[5] & 0x0001)
|
|
cfg |= Ext125;
|
|
if(ctlr->eeprom[5] & 0x0002)
|
|
cfg |= M64addren;
|
|
if((ctlr->eeprom[5] & 0x0004) && (r & Pci64det))
|
|
cfg |= Data64en;
|
|
if(ctlr->eeprom[5] & 0x0008)
|
|
cfg |= T64addren;
|
|
if(!(pcicfgr16(ctlr->pcidev, PciPCR) & 0x10))
|
|
cfg |= Mwidis;
|
|
if(ctlr->eeprom[5] & 0x0020)
|
|
cfg |= Mrmdis;
|
|
if(ctlr->eeprom[5] & 0x0080)
|
|
cfg |= Mode1000;
|
|
if(ctlr->eeprom[5] & 0x0200)
|
|
cfg |= Tbien|Mode1000;
|
|
/*
|
|
* What about RO bits we might have destroyed with Rst?
|
|
* What about Exd, Tmrtest, Extstsen, Pintctl?
|
|
* Why does it think it has detected a 64-bit bus when
|
|
* it hasn't?
|
|
*/
|
|
#else
|
|
// r = csr32r(ctlr, Cfg);
|
|
// r &= ~(Mode1000|T64addren|Data64en|M64addren);
|
|
// csr32w(ctlr, Cfg, r);
|
|
// csr32w(ctlr, Cfg, 0x2000);
|
|
#endif /* notdef */
|
|
ctlr->cfg = csr32r(ctlr, Cfg);
|
|
print("cfg %8.8uX pcicfg %8.8uX\n", ctlr->cfg, pcicfgr32(ctlr->pcidev, PciPCR));
|
|
ctlr->cfg &= ~(T64addren|Data64en|M64addren);
|
|
csr32w(ctlr, Cfg, ctlr->cfg);
|
|
csr32w(ctlr, Mibc, Aclr|Frz);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
dp83820pci(void)
|
|
{
|
|
void *mem;
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != Pcibcnet || p->ccru != Pciscether)
|
|
continue;
|
|
|
|
switch((p->did<<16)|p->vid){
|
|
default:
|
|
continue;
|
|
case (0x0022<<16)|0x100B: /* DP83820 (Gig-NIC) */
|
|
break;
|
|
}
|
|
|
|
mem = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size);
|
|
if(mem == 0){
|
|
print("DP83820: can't map %8.8luX\n", p->mem[1].bar);
|
|
continue;
|
|
}
|
|
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
ctlr->port = p->mem[1].bar & ~0x0F;
|
|
ctlr->pcidev = p;
|
|
ctlr->id = (p->did<<16)|p->vid;
|
|
|
|
ctlr->nic = mem;
|
|
if(dp83820reset(ctlr)){
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
|
|
if(dp83820ctlrhead != nil)
|
|
dp83820ctlrtail->next = ctlr;
|
|
else
|
|
dp83820ctlrhead = ctlr;
|
|
dp83820ctlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
static int
|
|
dp83820pnp(Ether* edev)
|
|
{
|
|
int i;
|
|
Ctlr *ctlr;
|
|
uchar ea[Eaddrlen];
|
|
|
|
if(dp83820ctlrhead == nil)
|
|
dp83820pci();
|
|
|
|
/*
|
|
* Any adapter matches if no edev->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = dp83820ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
if(edev->port == 0 || edev->port == ctlr->port){
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pcidev->intl;
|
|
edev->tbdf = ctlr->pcidev->tbdf;
|
|
edev->mbps = 1000;
|
|
|
|
/*
|
|
* Check if the adapter's station address is to be overridden.
|
|
* If not, read it from the EEPROM and set in ether->ea prior to
|
|
* loading the station address in the hardware.
|
|
*/
|
|
memset(ea, 0, Eaddrlen);
|
|
if(memcmp(ea, edev->ea, Eaddrlen) == 0)
|
|
for(i = 0; i < Eaddrlen/2; i++){
|
|
edev->ea[2*i] = ctlr->eeprom[0x0C-i];
|
|
edev->ea[2*i+1] = ctlr->eeprom[0x0C-i]>>8;
|
|
}
|
|
|
|
edev->attach = dp83820attach;
|
|
edev->transmit = dp83820transmit;
|
|
edev->interrupt = dp83820interrupt;
|
|
edev->ifstat = dp83820ifstat;
|
|
|
|
edev->arg = edev;
|
|
edev->promiscuous = dp83820promiscuous;
|
|
edev->multicast = dp83820multicast;
|
|
edev->shutdown = dp83820shutdown;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
etherdp83820link(void)
|
|
{
|
|
addethercard("DP83820", dp83820pnp);
|
|
}
|