c3589ef3cf
This used to be a internal function, but virtio uses multiple structures with the same cap type to indicate the location of various register blocks in the pci bars so export it.
303 lines
8.1 KiB
C
303 lines
8.1 KiB
C
/*
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* PCI support code.
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*/
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enum { /* type 0 & type 1 pre-defined header */
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PciVID = 0x00, /* vendor ID */
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PciDID = 0x02, /* device ID */
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PciPCR = 0x04, /* command */
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PciPSR = 0x06, /* status */
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PciRID = 0x08, /* revision ID */
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PciCCRp = 0x09, /* programming interface class code */
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PciCCRu = 0x0A, /* sub-class code */
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PciCCRb = 0x0B, /* base class code */
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PciCLS = 0x0C, /* cache line size */
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PciLTR = 0x0D, /* latency timer */
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PciHDT = 0x0E, /* header type */
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PciBST = 0x0F, /* BIST */
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PciBAR0 = 0x10, /* base address */
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PciBAR1 = 0x14,
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PciCAP = 0x34, /* capabilities pointer */
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PciINTL = 0x3C, /* interrupt line */
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PciINTP = 0x3D, /* interrupt pin */
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};
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/* ccrb (base class code) values; controller types */
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enum {
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Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
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Pcibcstore = 1, /* mass storage */
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Pcibcnet = 2, /* network */
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Pcibcdisp = 3, /* display */
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Pcibcmmedia = 4, /* multimedia */
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Pcibcmem = 5, /* memory */
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Pcibcbridge = 6, /* bridge */
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Pcibccomm = 7, /* simple comms (e.g., serial) */
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Pcibcbasesys = 8, /* base system */
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Pcibcinput = 9, /* input */
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Pcibcdock = 0xa, /* docking stations */
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Pcibcproc = 0xb, /* processors */
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Pcibcserial = 0xc, /* serial bus (e.g., USB) */
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Pcibcwireless = 0xd, /* wireless */
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Pcibcintell = 0xe, /* intelligent i/o */
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Pcibcsatcom = 0xf, /* satellite comms */
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Pcibccrypto = 0x10, /* encryption/decryption */
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Pcibcdacq = 0x11, /* data acquisition & signal proc. */
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};
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/* ccru (sub-class code) values; common cases only */
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enum {
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/* mass storage */
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Pciscscsi = 0, /* SCSI */
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Pciscide = 1, /* IDE (ATA) */
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/* network */
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Pciscether = 0, /* Ethernet */
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/* display */
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Pciscvga = 0, /* VGA */
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Pciscxga = 1, /* XGA */
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Pcisc3d = 2, /* 3D */
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/* bridges */
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Pcischostpci = 0, /* host/pci */
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Pciscpcicpci = 1, /* pci/pci */
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/* simple comms */
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Pciscserial = 0, /* 16450, etc. */
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Pciscmultiser = 1, /* multiport serial */
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/* serial bus */
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Pciscusb = 3, /* USB */
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};
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enum { /* type 0 pre-defined header */
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PciCIS = 0x28, /* cardbus CIS pointer */
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PciSVID = 0x2C, /* subsystem vendor ID */
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PciSID = 0x2E, /* subsystem ID */
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PciEBAR0 = 0x30, /* expansion ROM base address */
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PciMGNT = 0x3E, /* burst period length */
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PciMLT = 0x3F, /* maximum latency between bursts */
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};
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enum { /* type 1 pre-defined header */
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PciPBN = 0x18, /* primary bus number */
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PciSBN = 0x19, /* secondary bus number */
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PciUBN = 0x1A, /* subordinate bus number */
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PciSLTR = 0x1B, /* secondary latency timer */
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PciIBR = 0x1C, /* I/O base */
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PciILR = 0x1D, /* I/O limit */
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PciSPSR = 0x1E, /* secondary status */
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PciMBR = 0x20, /* memory base */
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PciMLR = 0x22, /* memory limit */
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PciPMBR = 0x24, /* prefetchable memory base */
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PciPMLR = 0x26, /* prefetchable memory limit */
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PciPUBR = 0x28, /* prefetchable base upper 32 bits */
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PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
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PciIUBR = 0x30, /* I/O base upper 16 bits */
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PciIULR = 0x32, /* I/O limit upper 16 bits */
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PciEBAR1 = 0x38, /* expansion ROM base address */
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PciBCR = 0x3E, /* bridge control register */
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};
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enum { /* type 2 pre-defined header */
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PciCBExCA = 0x10,
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PciCBSPSR = 0x16,
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PciCBPBN = 0x18, /* primary bus number */
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PciCBSBN = 0x19, /* secondary bus number */
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PciCBUBN = 0x1A, /* subordinate bus number */
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PciCBSLTR = 0x1B, /* secondary latency timer */
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PciCBMBR0 = 0x1C,
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PciCBMLR0 = 0x20,
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PciCBMBR1 = 0x24,
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PciCBMLR1 = 0x28,
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PciCBIBR0 = 0x2C, /* I/O base */
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PciCBILR0 = 0x30, /* I/O limit */
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PciCBIBR1 = 0x34, /* I/O base */
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PciCBILR1 = 0x38, /* I/O limit */
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PciCBSVID = 0x40, /* subsystem vendor ID */
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PciCBSID = 0x42, /* subsystem ID */
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PciCBLMBAR = 0x44, /* legacy mode base address */
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};
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/* capabilities */
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enum {
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PciCapPMG = 0x01, /* power management */
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PciCapAGP = 0x02,
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PciCapVPD = 0x03, /* vital product data */
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PciCapSID = 0x04, /* slot id */
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PciCapMSI = 0x05,
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PciCapCHS = 0x06, /* compact pci hot swap */
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PciCapPCIX = 0x07,
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PciCapHTC = 0x08, /* hypertransport irq conf */
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PciCapVND = 0x09, /* vendor specific information */
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PciCapPCIe = 0x10,
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PciCapMSIX = 0x11,
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PciCapSATA = 0x12,
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PciCapHSW = 0x0c, /* hot swap */
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};
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enum {
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/* bar bits */
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Barioaddr = 1<<0, /* vs. memory addr */
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Barwidthshift = 1,
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Barwidthmask = 3,
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Barwidth32 = 0,
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Barwidth64 = 2,
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Barprefetch = 1<<3,
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};
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enum
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{ /* command register */
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IOen = (1<<0),
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MEMen = (1<<1),
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MASen = (1<<2),
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MemWrInv = (1<<4),
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PErrEn = (1<<6),
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SErrEn = (1<<8),
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};
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typedef struct Pcidev Pcidev;
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struct Pcidev
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{
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int tbdf; /* type+bus+device+function */
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ushort vid; /* vendor ID */
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ushort did; /* device ID */
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ushort pcr;
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uchar rid;
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uchar ccrp;
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uchar ccru;
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uchar ccrb;
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uchar cls;
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uchar ltr;
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uchar intl; /* interrupt line */
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struct {
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uvlong bar; /* base address */
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int size;
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} mem[6];
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struct { /* expansion rom bar */
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uvlong bar;
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int size;
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} rom;
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struct { /* 32-bit io and memory windows */
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uvlong bar;
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int size;
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} ioa, mema;
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struct { /* 64-bit prefechable memory window */
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uvlong bar;
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uvlong size;
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} prefa;
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Pcidev* list;
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Pcidev* link; /* next device on this bno */
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Pcidev* parent; /* up a bus */
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Pcidev* bridge; /* down a bus */
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int pmrb; /* power management register block */
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int msi; /* MSI capability register block */
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};
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enum {
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/* vendor ids */
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Vintel = 0x8086,
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Vmyricom= 0x14c1,
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Vatiamd = 0x1002,
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Vjmicron= 0x197b,
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Vmarvell= 0x1b4b,
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Vnvidia = 0x10de,
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Vrealtek= 0x10ec,
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};
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enum
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{
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MaxFNO = 7,
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MaxUBN = 255,
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};
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extern int pcimaxdno;
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extern void pcidevfree(Pcidev* pcidev);
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extern int pcicfgr32(Pcidev* pcidev, int rno);
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extern void pcicfgw32(Pcidev* pcidev, int rno, int data);
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extern int pcicfgr16(Pcidev* pcidev, int rno);
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extern void pcicfgw16(Pcidev* pcidev, int rno, int data);
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extern int pcicfgr8(Pcidev* pcidev, int rno);
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extern void pcicfgw8(Pcidev* pcidev, int rno, int data);
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extern int pciscan(int bno, Pcidev **list, Pcidev *parent);
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extern void pcibusmap(Pcidev *root, uvlong *pmema, ulong *pioa, int wrreg);
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extern void pcibussize(Pcidev *root, uvlong *msize, ulong *iosize);
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extern Pcidev* pcimatch(Pcidev* prev, int vid, int did);
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extern Pcidev* pcimatchtbdf(int tbdf);
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extern int pcibarsize(Pcidev *, int rno);
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extern void pcisetbar(Pcidev *, int, uvlong);
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extern uchar pciipin(Pcidev *pci, uchar pin);
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extern void pcisetioe(Pcidev* p);
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extern void pciclrioe(Pcidev* p);
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extern void pcisetbme(Pcidev* p);
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extern void pciclrbme(Pcidev* p);
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extern void pcisetmwi(Pcidev* p);
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extern void pciclrmwi(Pcidev* p);
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extern int pcicap(Pcidev *p, int cap);
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extern int pcihtcap(Pcidev *p, int cap);
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extern int pcienumcaps(Pcidev *p, int (*fmatch)(Pcidev*, int, int, int), int arg);
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extern int pcimsienable(Pcidev *p, uvlong addr, ulong data);
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extern int pcimsidisable(Pcidev *p);
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extern int pcigetpms(Pcidev* p);
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extern int pcisetpms(Pcidev* p, int state);
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extern void pcienable(Pcidev *p);
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extern void pcidisable(Pcidev *p);
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extern void pcihinv(Pcidev* p);
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extern void pcireset(void);
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enum {
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BusCBUS = 0, /* Corollary CBUS */
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BusCBUSII, /* Corollary CBUS II */
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BusEISA, /* Extended ISA */
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BusFUTURE, /* IEEE Futurebus */
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BusINTERN, /* Internal bus */
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BusISA, /* Industry Standard Architecture */
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BusMBI, /* Multibus I */
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BusMBII, /* Multibus II */
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BusMCA, /* Micro Channel Architecture */
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BusMPI, /* MPI */
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BusMPSA, /* MPSA */
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BusNUBUS, /* Apple Macintosh NuBus */
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BusPCI, /* Peripheral Component Interconnect */
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BusPCMCIA, /* PC Memory Card International Association */
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BusTC, /* DEC TurboChannel */
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BusVL, /* VESA Local bus */
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BusVME, /* VMEbus */
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BusXPRESS, /* Express System Bus */
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};
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#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
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#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
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#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
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#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
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#define BUSTYPE(tbdf) ((tbdf)>>24)
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#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
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extern int tbdffmt(Fmt*);
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#pragma varargck type "T" int
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#pragma varargck type "T" uint
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